From 82f131a017f27462162062bd9ad0d4cea3166c61 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 2 Oct 2011 21:08:12 +0000 Subject: [PATCH] Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrArithmetic.td | 53 +++++++++++++-------- lib/Target/X86/X86InstrInfo.td | 26 +++++------ test/MC/Disassembler/X86/intel-syntax.txt | 57 +++++++++++++++++++++++ test/MC/Disassembler/X86/simple-tests.txt | 54 +++++++++++++++++++++ test/MC/Disassembler/X86/x86-32.txt | 57 +++++++++++++++++++++++ 5 files changed, 215 insertions(+), 32 deletions(-) diff --git a/lib/Target/X86/X86InstrArithmetic.td b/lib/Target/X86/X86InstrArithmetic.td index c7eb18d8b9e..6d2c53495cf 100644 --- a/lib/Target/X86/X86InstrArithmetic.td +++ b/lib/Target/X86/X86InstrArithmetic.td @@ -866,11 +866,10 @@ class BinOpMI8_F opcode, string mnemonic, X86TypeInfo typeinfo, - Register areg> + Register areg, string operands> : ITy { + mnemonic, operands, []> { let ImmT = typeinfo.ImmEncoding; let Uses = [areg]; let Defs = [areg]; @@ -935,10 +934,14 @@ multiclass ArithBinOp_RF BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, def #NAME#32mi : BinOpMI_RMW; def #NAME#64mi32 : BinOpMI_RMW; - def #NAME#8i8 : BinOpAI; - def #NAME#16i16 : BinOpAI; - def #NAME#32i32 : BinOpAI; - def #NAME#64i32 : BinOpAI; + def #NAME#8i8 : BinOpAI; + def #NAME#16i16 : BinOpAI; + def #NAME#32i32 : BinOpAI; + def #NAME#64i32 : BinOpAI; } } @@ -1002,10 +1005,14 @@ multiclass ArithBinOp_RFF BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, def #NAME#32mi : BinOpMI_RMW_FF; def #NAME#64mi32 : BinOpMI_RMW_FF; - def #NAME#8i8 : BinOpAI; - def #NAME#16i16 : BinOpAI; - def #NAME#32i32 : BinOpAI; - def #NAME#64i32 : BinOpAI; + def #NAME#8i8 : BinOpAI; + def #NAME#16i16 : BinOpAI; + def #NAME#32i32 : BinOpAI; + def #NAME#64i32 : BinOpAI; } } @@ -1065,10 +1072,14 @@ multiclass ArithBinOp_F BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, def #NAME#32mi : BinOpMI_F; def #NAME#64mi32 : BinOpMI_F; - def #NAME#8i8 : BinOpAI; - def #NAME#16i16 : BinOpAI; - def #NAME#32i32 : BinOpAI; - def #NAME#64i32 : BinOpAI; + def #NAME#8i8 : BinOpAI; + def #NAME#16i16 : BinOpAI; + def #NAME#32i32 : BinOpAI; + def #NAME#64i32 : BinOpAI; } } @@ -1126,9 +1137,13 @@ let Defs = [EFLAGS] in { def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>; def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>; - def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL>; - def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX>; - def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX>; - def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX>; + def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL, + "{$src, %al|AL, $src}">; + def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX, + "{$src, %ax|AX, $src}">; + def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX, + "{$src, %eax|EAX, $src}">; + def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX, + "{$src, %rax|RAX, $src}">; } diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 329057fef23..e60b867d8d6 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -877,22 +877,22 @@ def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a /// 32-bit offset from the PC. These are only valid in x86-32 mode. def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src), - "mov{b}\t{$src, %al|%al, $src}", []>, + "mov{b}\t{$src, %al|AL, $src}", []>, Requires<[In32BitMode]>; def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src), - "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize, + "mov{w}\t{$src, %ax|AL, $src}", []>, OpSize, Requires<[In32BitMode]>; def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), - "mov{l}\t{$src, %eax|%eax, $src}", []>, + "mov{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In32BitMode]>; def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins), - "mov{b}\t{%al, $dst|$dst, %al}", []>, + "mov{b}\t{%al, $dst|$dst, AL}", []>, Requires<[In32BitMode]>; def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins), - "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize, + "mov{w}\t{%ax, $dst|$dst, AL}", []>, OpSize, Requires<[In32BitMode]>; def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins), - "mov{l}\t{%eax, $dst|$dst, %eax}", []>, + "mov{l}\t{%eax, $dst|$dst, EAX}", []>, Requires<[In32BitMode]>; // FIXME: These definitions are utterly broken @@ -901,13 +901,13 @@ def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins), // in question. /* def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src), - "mov{q}\t{$src, %rax|%rax, $src}", []>; + "mov{q}\t{$src, %rax|RAX, $src}", []>; def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src), - "mov{q}\t{$src, %rax|%rax, $src}", []>; + "mov{q}\t{$src, %rax|RAX, $src}", []>; def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins), - "mov{q}\t{%rax, $dst|$dst, %rax}", []>; + "mov{q}\t{%rax, $dst|$dst, RAX}", []>; def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins), - "mov{q}\t{%rax, $dst|$dst, %rax}", []>; + "mov{q}\t{%rax, $dst|$dst, RAX}", []>; */ @@ -1153,11 +1153,11 @@ def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), } def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), - "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize; + "xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize; def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), - "xchg{l}\t{$src, %eax|%eax, $src}", []>; + "xchg{l}\t{$src, %eax|EAX, $src}", []>; def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), - "xchg{q}\t{$src, %rax|%rax, $src}", []>; + "xchg{q}\t{$src, %rax|RAX, $src}", []>; diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index c04dcd099ba..54b242d7b2e 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -20,3 +20,60 @@ # CHECK: in AL, DX 0xec + +# CHECK: nop +0x90 + +# CHECK: xchg EAX, R8D +0x41 0x90 + +# CHECK: xchg RAX, R8 +0x49 0x90 + +# CHECK: add AL, 0 +0x04 0x00 + +# CHECK: add AX, 0 +0x66 0x05 0x00 0x00 + +# CHECK: add EAX, 0 +0x05 0x00 0x00 0x00 0x00 + +# CHECK: add RAX, 0 +0x48 0x05 0x00 0x00 0x00 0x00 + +# CHECK: adc AL, 0 +0x14 0x00 + +# CHECK: adc AX, 0 +0x66 0x15 0x00 0x00 + +# CHECK: adc EAX, 0 +0x15 0x00 0x00 0x00 0x00 + +# CHECK: adc RAX, 0 +0x48 0x15 0x00 0x00 0x00 0x00 + +# CHECK: cmp AL, 0 +0x3c 0x00 + +# CHECK: cmp AX, 0 +0x66 0x3d 0x00 0x00 + +# CHECK: cmp EAX, 0 +0x3d 0x00 0x00 0x00 0x00 + +# CHECK: cmp RAX, 0 +0x48 0x3d 0x00 0x00 0x00 0x00 + +# CHECK: test AL, 0 +0xa8 0x00 + +# CHECK: test AX, 0 +0x66 0xa9 0x00 0x00 + +# CHECK: test EAX, 0 +0xa9 0x00 0x00 0x00 0x00 + +# CHECK: test RAX, 0 +0x48 0xa9 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index fc64d64687c..cfaeb06d724 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -309,5 +309,59 @@ # CHECK: invvpid (%rax), %rax 0x66 0x0f 0x38 0x81 0x00 +# CHECK: nop +0x90 + # CHECK: xchgl %r8d, %eax 0x41 0x90 + +# CHECK: xchgq %r8, %rax +0x49 0x90 + +# CHECK: addb $0, %al +0x04 0x00 + +# CHECK: addw $0, %ax +0x66 0x05 0x00 0x00 + +# CHECK: addl $0, %eax +0x05 0x00 0x00 0x00 0x00 + +# CHECK: addq $0, %rax +0x48 0x05 0x00 0x00 0x00 0x00 + +# CHECK: adcb $0, %al +0x14 0x00 + +# CHECK: adcw $0, %ax +0x66 0x15 0x00 0x00 + +# CHECK: adcl $0, %eax +0x15 0x00 0x00 0x00 0x00 + +# CHECK: adcq $0, %rax +0x48 0x15 0x00 0x00 0x00 0x00 + +# CHECK: cmpb $0, %al +0x3c 0x00 + +# CHECK: cmpw $0, %ax +0x66 0x3d 0x00 0x00 + +# CHECK: cmpl $0, %eax +0x3d 0x00 0x00 0x00 0x00 + +# CHECK: cmpq $0, %rax +0x48 0x3d 0x00 0x00 0x00 0x00 + +# CHECK: testb $0, %al +0xa8 0x00 + +# CHECK: testw $0, %ax +0x66 0xa9 0x00 0x00 + +# CHECK: testl $0, %eax +0xa9 0x00 0x00 0x00 0x00 + +# CHECK: testq $0, %rax +0x48 0xa9 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index 75e6b169864..c0164cbbcfb 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -327,3 +327,60 @@ # CHECK: invvpid (%eax), %eax 0x66 0x0f 0x38 0x81 0x00 + +# CHECK: nop +0x90 + +# CHECK: addb $0, %al +0x04 0x00 + +# CHECK: addw $0, %ax +0x66 0x05 0x00 0x00 + +# CHECK: addl $0, %eax +0x05 0x00 0x00 0x00 0x00 + +# CHECK: adcb $0, %al +0x14 0x00 + +# CHECK: adcw $0, %ax +0x66 0x15 0x00 0x00 + +# CHECK: adcl $0, %eax +0x15 0x00 0x00 0x00 0x00 + +# CHECK: cmpb $0, %al +0x3c 0x00 + +# CHECK: cmpw $0, %ax +0x66 0x3d 0x00 0x00 + +# CHECK: cmpl $0, %eax +0x3d 0x00 0x00 0x00 0x00 + +# CHECK: testb $0, %al +0xa8 0x00 + +# CHECK: testw $0, %ax +0x66 0xa9 0x00 0x00 + +# CHECK: testl $0, %eax +0xa9 0x00 0x00 0x00 0x00 + +# CHECK: movb 0, %al +0xa0 0x00 0x00 0x00 0x00 + +# CHECK: movw 0, %ax +0x66 0xa1 0x00 0x00 0x00 0x00 + +# CHECK: movl 0, %eax +0xa1 0x00 0x00 0x00 0x00 + +# CHECK: movb %al, 0 +0xa2 0x00 0x00 0x00 0x00 + +# CHECK: movw %ax, 0 +0x66 0xa3 0x00 0x00 0x00 0x00 + +# CHECK: movl %eax, 0 +0xa3 0x00 0x00 0x00 0x00