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rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-01-06 23:38:27 +00:00
parent 9e7aba2739
commit 834f1ce031
26 changed files with 72 additions and 61 deletions
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20
include/llvm/Target/TargetInstrInfo.h
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@ -48,7 +48,11 @@ const unsigned M_CALL_FLAG = 1 << 1;
const unsigned M_RET_FLAG = 1 << 2;
const unsigned M_BARRIER_FLAG = 1 << 3;
const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
const unsigned M_LOAD_FLAG = 1 << 5;
/// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads
/// from memory. This should only be set on instructions that load a value from
/// memory and return it in their only virtual register definition.
const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
/// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
/// modify memory. Instructions with this flag set are not necessarily simple
@ -184,6 +188,17 @@ public:
/// findTiedToSrcOperand - Returns the operand that is tied to the specified
/// dest operand. Returns -1 if there isn't one.
int findTiedToSrcOperand(unsigned OpNum) const;
/// isSimpleLoad - Return true for instructions that are simple loads from
/// memory. This should only be set on instructions that load a value from
/// memory and return it in their only virtual register definition.
/// Instructions that return a value loaded from memory and then modified in
/// some way should not return true for this.
bool isSimpleLoad() const {
return Flags & M_SIMPLE_LOAD_FLAG;
}
};
@ -279,9 +294,6 @@ public:
bool isCall(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_CALL_FLAG;
}
bool isLoad(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_LOAD_FLAG;
}
/// mayStore - Return true if this instruction could possibly modify memory.
/// Instructions with this flag set are not necessarily simple store

2
lib/CodeGen/BranchFolding.cpp
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@ -353,7 +353,7 @@ static unsigned EstimateRuntime(MachineBasicBlock::iterator I,
const TargetInstrDescriptor &TID = TII->get(I->getOpcode());
if (TID.Flags & M_CALL_FLAG)
Time += 10;
else if (TID.Flags & (M_LOAD_FLAG|M_MAY_STORE_FLAG))
else if (TID.isSimpleLoad() || (TID.Flags & M_MAY_STORE_FLAG))
Time += 2;
else
++Time;

9
lib/CodeGen/LiveIntervalAnalysis.cpp
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@ -618,7 +618,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
if ((TID->Flags & M_IMPLICIT_DEF_FLAG) ||
tii_->isTriviallyReMaterializable(MI)) {
isLoad = TID->Flags & M_LOAD_FLAG;
isLoad = TID->isSimpleLoad();
return true;
}
@ -1226,7 +1226,7 @@ addIntervalsForSpills(const LiveInterval &li,
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
(DefIsReMat && (ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG));
(DefIsReMat && (ReMatDefMI->getInstrDescriptor()->isSimpleLoad()));
bool IsFirstRange = true;
for (LiveInterval::Ranges::const_iterator
I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
@ -1308,7 +1308,7 @@ addIntervalsForSpills(const LiveInterval &li,
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
(DefIsReMat && (ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG));
(DefIsReMat && ReMatDefMI->getInstrDescriptor()->isSimpleLoad());
rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
@ -1423,8 +1423,7 @@ addIntervalsForSpills(const LiveInterval &li,
int LdSlot = 0;
bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
// If the rematerializable def is a load, also try to fold it.
if (isLoadSS ||
(ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG))
if (isLoadSS || ReMatDefMI->getInstrDescriptor()->isSimpleLoad())
Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
Ops, isLoadSS, LdSlot, VReg);
}

2
lib/Target/ARM/ARMInstrInfo.cpp
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@ -202,7 +202,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
unsigned NumOps = TID->numOperands;
bool isLoad = (TID->Flags & M_LOAD_FLAG) != 0;
bool isLoad = TID->isSimpleLoad();
const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
const MachineOperand &Base = MI->getOperand(2);
const MachineOperand &Offset = MI->getOperand(NumOps-3);

10
lib/Target/ARM/ARMInstrInfo.td
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@ -684,7 +684,7 @@ def PICADD : AXI1<0x0, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
let isLoad = 1, AddedComplexity = 10 in {
let isSimpleLoad = 1, AddedComplexity = 10 in {
def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
[(set GPR:$dst, (load addrmodepc:$addr))]>;
@ -738,7 +738,7 @@ let isReturn = 1, isTerminator = 1 in
// FIXME: remove when we have a way to marking a MI with these properties.
// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
// operand list.
let isLoad = 1, isReturn = 1, isTerminator = 1 in
let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in
def LDM_RET : AXI4<0x0, (outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
@ -802,7 +802,7 @@ let isBranch = 1, isTerminator = 1 in {
//
// Load
let isLoad = 1 in {
let isSimpleLoad = 1 in {
def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
"ldr", " $dst, $addr",
[(set GPR:$dst, (load addrmode2:$addr))]>;
@ -875,7 +875,7 @@ def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb),
def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdFrm,
"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
} // isLoad
} // isSimpleLoad
// Store
def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
@ -939,7 +939,7 @@ def STRB_POST: AI2po<0x1, (outs GPR:$base_wb),
//
// FIXME: $dst1 should be a def.
let isLoad = 1 in
let isSimpleLoad = 1 in
def LDM : AXI4<0x0, (outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
LdFrm, "ldm${p}${addr:submode} $addr, $dst1",

8
lib/Target/ARM/ARMInstrThumb.td
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@ -188,7 +188,7 @@ let isReturn = 1, isTerminator = 1 in {
}
// FIXME: remove when we have a way to marking a MI with these properties.
let isLoad = 1, isReturn = 1, isTerminator = 1 in
let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in
def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
"pop $dst1", []>;
@ -237,7 +237,7 @@ let isBranch = 1, isTerminator = 1 in
// Load Store Instructions.
//
let isLoad = 1 in {
let isSimpleLoad = 1 in {
def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr),
"ldr $dst, $addr",
[(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
@ -276,7 +276,7 @@ def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr),
let isReMaterializable = 1 in
def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
"ldr $dst, $addr", []>;
} // isLoad
} // isSimpleLoad
def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
"str $src, $addr",
@ -307,7 +307,7 @@ def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
// TODO: A7-44: LDMIA - load multiple
let isLoad = 1 in
let isSimpleLoad = 1 in
def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
"pop $dst1", []>;

8
lib/Target/ARM/ARMInstrVFP.td
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@ -88,7 +88,7 @@ def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
// Load / store Instructions.
//
let isLoad = 1 in {
let isSimpleLoad = 1 in {
def FLDD : ADI5<(outs DPR:$dst), (ins addrmode5:$addr),
"fldd", " $dst, $addr",
[(set DPR:$dst, (load addrmode5:$addr))]>;
@ -96,7 +96,7 @@ def FLDD : ADI5<(outs DPR:$dst), (ins addrmode5:$addr),
def FLDS : ASI5<(outs SPR:$dst), (ins addrmode5:$addr),
"flds", " $dst, $addr",
[(set SPR:$dst, (load addrmode5:$addr))]>;
} // isLoad
} // isSimpleLoad
def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr),
"fstd", " $src, $addr",
@ -110,7 +110,7 @@ def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr),
// Load / store multiple Instructions.
//
let isLoad = 1 in {
let isSimpleLoad = 1 in {
def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
variable_ops),
"fldm${addr:submode}d${p} ${addr:base}, $dst1",
@ -120,7 +120,7 @@ def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
variable_ops),
"fldm${addr:submode}s${p} ${addr:base}, $dst1",
[]>;
} // isLoad
} // isSimpleLoad
let mayStore = 1 in {
def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,

4
lib/Target/ARM/ARMRegisterInfo.cpp
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@ -690,7 +690,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
}
unsigned Opcode = MI.getOpcode();
const TargetInstrDescriptor &Desc = TII.get(Opcode);
const TargetInstrDescriptor &Desc = *MI.getInstrDescriptor();
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
bool isSub = false;
@ -885,7 +885,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
assert(Offset && "This code isn't needed if offset already handled!");
if (isThumb) {
if (TII.isLoad(Opcode)) {
if (Desc.isSimpleLoad()) {
// Use the destination register to materialize sp + offset.
unsigned TmpReg = MI.getOperand(0).getReg();
bool UseRR = false;

2
lib/Target/Alpha/AlphaInstrFormats.td
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@ -41,7 +41,7 @@ class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern, InstrItinClass itin>
: InstAlpha<opcode, asmstr, itin> {
let Pattern = pattern;
let isLoad = load;
let isSimpleLoad = load;
let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
bits<5> Ra;

2
lib/Target/Alpha/AlphaInstrInfo.td
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@ -152,7 +152,7 @@ def IDEF_F64 : PseudoInstAlpha<(outs F8RC:$RA), (ins), ";#idef $RA",
def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>;
let isLoad = 1, hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {
let hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {
def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt),
"; ADJUP $amt",
[(callseq_start imm:$amt)], s_pseudo>;

2
lib/Target/CellSPU/SPUInstrInfo.td
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@ -47,7 +47,7 @@ def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$fi
// finally the X-form with the register-register.
//===----------------------------------------------------------------------===//
let isLoad = 1 in {
let isSimpleLoad = 1 in {
def LQDv16i8:
RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
"lqd\t$rT, $src", LoadStore,

2
lib/Target/IA64/IA64InstrInfo.td
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@ -558,7 +558,7 @@ let mayStore = 1 in {
"stf.spill [$dstPtr] = $value">, isM;
}
let isLoad = 1 in {
let isSimpleLoad = 1 in {
def LD1 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
"ld1 $dst = [$srcPtr]">, isM;
def LD2 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),

2
lib/Target/Mips/MipsInstrInfo.td
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@ -205,7 +205,7 @@ class LoadUpper<bits<6> op, string instr_asm>:
[], IIAlu>;
// Memory Load/Store
let isLoad = 1, hasDelaySlot = 1 in
let isSimpleLoad = 1, hasDelaySlot = 1 in
class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
FI< op,
(outs CPURegs:$dst),

2
lib/Target/PowerPC/PPCHazardRecognizers.cpp
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@ -72,7 +72,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
const TargetInstrDescriptor &TID = TII.get(Opcode);
isLoad = TID.Flags & M_LOAD_FLAG;
isLoad = TID.isSimpleLoad();
isStore = TID.Flags & M_MAY_STORE_FLAG;
unsigned TSFlags = TID.TSFlags;

6
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -365,7 +365,7 @@ def RLDICR : MDForm_1<30, 1,
// Sign extending loads.
let isLoad = 1, PPC970_Unit = 2 in {
let isSimpleLoad = 1, PPC970_Unit = 2 in {
def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
"lha $rD, $src", LdStLHA,
[(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
@ -394,7 +394,7 @@ def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
}
// Zero extending loads.
let isLoad = 1, PPC970_Unit = 2 in {
let isSimpleLoad = 1, PPC970_Unit = 2 in {
def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
"lbz $rD, $src", LdStGeneral,
[(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
@ -433,7 +433,7 @@ def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
// Full 8-byte loads.
let isLoad = 1, PPC970_Unit = 2 in {
let isSimpleLoad = 1, PPC970_Unit = 2 in {
def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
"ld $rD, $src", LdStLD,
[(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;

2
lib/Target/PowerPC/PPCInstrAltivec.td
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@ -202,7 +202,7 @@ def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB),
"mtvscr $vB", LdStGeneral,
[(int_ppc_altivec_mtvscr VRRC:$vB)]>;
let isLoad = 1, PPC970_Unit = 2 in { // Loads.
let isSimpleLoad = 1, PPC970_Unit = 2 in { // Loads.
def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src),
"lvebx $vD, $src", LdStGeneral,
[(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;

4
lib/Target/PowerPC/PPCInstrInfo.td
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@ -474,7 +474,7 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
//
// Unindexed (r+i) Loads.
let isLoad = 1, PPC970_Unit = 2 in {
let isSimpleLoad = 1, PPC970_Unit = 2 in {
def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
"lbz $rD, $src", LdStGeneral,
[(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
@ -531,7 +531,7 @@ def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
// Indexed (r+r) Loads.
//
let isLoad = 1, PPC970_Unit = 2 in {
let isSimpleLoad = 1, PPC970_Unit = 2 in {
def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
"lbzx $rD, $src", LdStGeneral,
[(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;

2
lib/Target/Target.td
View File

@ -190,7 +190,7 @@ class Instruction {
bit isIndirectBranch = 0; // Is this instruction an indirect branch?
bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
bit isLoad = 0; // Is this instruction a load instruction?
bit isSimpleLoad = 0; // Is this just a load instruction?
bit mayStore = 0; // Can this instruction modify memory?
bit isImplicitDef = 0; // Is this instruction an implicit def instruction?
bit isTwoAddress = 0; // Is this a two address instruction?

2
lib/Target/X86/X86InstrFPStack.td
View File

@ -346,7 +346,7 @@ def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
"fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
// Floating point loads & stores.
let isLoad = 1 in {
let isSimpleLoad = 1 in {
def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
[(set RFP32:$dst, (loadf32 addr:$src))]>;
let isReMaterializable = 1, mayHaveSideEffects = 1 in

4
lib/Target/X86/X86InstrInfo.td
View File

@ -586,7 +586,7 @@ def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
"mov{l}\t{$src, $dst|$dst, $src}",
[(store (i32 imm:$src), addr:$dst)]>;
let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
"mov{b}\t{$src, $dst|$dst, $src}",
[(set GR8:$dst, (load addr:$src))]>;
@ -2488,7 +2488,7 @@ def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
"mov{l}\t{$src, $dst|$dst, $src}", []>;
let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),

4
lib/Target/X86/X86InstrMMX.td
View File

@ -158,7 +158,7 @@ def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]
// Data Transfer Instructions
def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
"movd\t{$src, $dst|$dst, $src}", []>;
let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
"movd\t{$src, $dst|$dst, $src}", []>;
def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
@ -169,7 +169,7 @@ def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
"movq\t{$src, $dst|$dst, $src}", []>;
let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
"movq\t{$src, $dst|$dst, $src}",
[(set VR64:$dst, (load_mmx addr:$src))]>;

24
lib/Target/X86/X86InstrSSE.td
View File

@ -301,7 +301,7 @@ let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
// Move Instructions
def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
"movss\t{$src, $dst|$dst, $src}", []>;
let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
"movss\t{$src, $dst|$dst, $src}",
[(set FR32:$dst, (loadf32 addr:$src))]>;
@ -457,7 +457,7 @@ def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
// Alias instruction to load FR32 from f128mem using movaps. Upper bits are
// disregarded.
let isLoad = 1 in
let isSimpleLoad = 1 in
def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
"movaps\t{$src, $dst|$dst, $src}",
[(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
@ -634,7 +634,7 @@ defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
// Move Instructions
def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movaps\t{$src, $dst|$dst, $src}", []>;
let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"movaps\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
@ -645,7 +645,7 @@ def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movups\t{$src, $dst|$dst, $src}", []>;
let isLoad = 1 in
let isSimpleLoad = 1 in
def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"movups\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (loadv4f32 addr:$src))]>;
@ -654,7 +654,7 @@ def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
[(store (v4f32 VR128:$src), addr:$dst)]>;
// Intrinsic forms of MOVUPS load and store
let isLoad = 1 in
let isSimpleLoad = 1 in
def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"movups\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
@ -1003,7 +1003,7 @@ def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
// Move Instructions
def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
"movsd\t{$src, $dst|$dst, $src}", []>;
let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
"movsd\t{$src, $dst|$dst, $src}",
[(set FR64:$dst, (loadf64 addr:$src))]>;
@ -1153,7 +1153,7 @@ def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
// Alias instruction to load FR64 from f128mem using movapd. Upper bits are
// disregarded.
let isLoad = 1 in
let isSimpleLoad = 1 in
def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
"movapd\t{$src, $dst|$dst, $src}",
[(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
@ -1330,7 +1330,7 @@ defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
// Move Instructions
def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movapd\t{$src, $dst|$dst, $src}", []>;
let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"movapd\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
@ -1341,7 +1341,7 @@ def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movupd\t{$src, $dst|$dst, $src}", []>;
let isLoad = 1 in
let isSimpleLoad = 1 in
def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"movupd\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (loadv2f64 addr:$src))]>;
@ -1704,14 +1704,14 @@ let isTwoAddress = 1 in {
// Move Instructions
def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movdqa\t{$src, $dst|$dst, $src}", []>;
let isLoad = 1 in
let isSimpleLoad = 1 in
def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
"movdqa\t{$src, $dst|$dst, $src}",
[/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
"movdqa\t{$src, $dst|$dst, $src}",
[/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
let isLoad = 1 in
let isSimpleLoad = 1 in
def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
"movdqu\t{$src, $dst|$dst, $src}",
[/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
@ -1722,7 +1722,7 @@ def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
XS, Requires<[HasSSE2]>;
// Intrinsic forms of MOVDQU load and store
let isLoad = 1 in
let isSimpleLoad = 1 in
def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
"movdqu\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,

2
lib/Target/X86/X86InstrX86-64.td
View File

@ -210,7 +210,7 @@ def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
[(set GR64:$dst, i64immSExt32:$src)]>;
}
let isLoad = 1 in
let isSimpleLoad = 1 in
def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"mov{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (load addr:$src))]>;

2
utils/TableGen/CodeGenInstruction.cpp
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@ -84,7 +84,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
isIndirectBranch = R->getValueAsBit("isIndirectBranch");
isBarrier = R->getValueAsBit("isBarrier");
isCall = R->getValueAsBit("isCall");
isLoad = R->getValueAsBit("isLoad");
isSimpleLoad = R->getValueAsBit("isSimpleLoad");
mayStore = R->getValueAsBit("mayStore");
isImplicitDef= R->getValueAsBit("isImplicitDef");
bool isTwoAddress = R->getValueAsBit("isTwoAddress");

2
utils/TableGen/CodeGenInstruction.h
View File

@ -94,7 +94,7 @@ namespace llvm {
bool isIndirectBranch;
bool isBarrier;
bool isCall;
bool isLoad;
bool isSimpleLoad;
bool mayStore;
bool isImplicitDef;
bool isPredicable;

4
utils/TableGen/InstrInfoEmitter.cpp
View File

@ -210,7 +210,7 @@ void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst,
}
// These two override everything.
isLoad = Inst.isLoad;
isLoad = Inst.isSimpleLoad;
NeverHasSideEffects = Inst.neverHasSideEffects;
#if 0
@ -308,7 +308,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
if (Inst.isCall) OS << "|M_CALL_FLAG";
if (isLoad) OS << "|M_LOAD_FLAG";
if (isLoad) OS << "|M_SIMPLE_LOAD_FLAG";
if (mayStore) OS << "|M_MAY_STORE_FLAG";
if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG";
if (Inst.isPredicable) OS << "|M_PREDICABLE";