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Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
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parent
f83f0f8246
commit
83a8031336
include/llvm/MC
lib
utils/TableGen
@ -477,6 +477,14 @@ public:
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return Flags & (1 << MCID::UsesCustomInserter);
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}
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/// hasPostISelHook - Return true if this instruction requires *adjustment*
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/// after instruction selection by calling a target hook. For example, this
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/// can be used to fill in ARM 's' optional operand depending on whether
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/// the conditional flag register is used.
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bool hasPostISelHook() const {
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return Flags & (1 << MCID::HasPostISelHook);
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}
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/// isRematerializable - Returns true if this instruction is a candidate for
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/// remat. This flag is deprecated, please don't use it anymore. If this
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/// flag is set, the isReallyTriviallyReMaterializable() method is called to
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@ -763,7 +763,8 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
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}
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// Run post-isel target hook to adjust this instruction if needed.
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TLI->AdjustInstrPostInstrSelection(MI, Node);
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if (II.hasPostISelHook())
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TLI->AdjustInstrPostInstrSelection(MI, Node);
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}
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/// EmitSpecialNode - Generate machine code for a target-independent node and
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@ -179,7 +179,12 @@ TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
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SDNode *Node) const {
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// Do nothing unless the target overrides it.
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#ifndef NDEBUG
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dbgs() << "If a target marks an instruction with "
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"'hasPostISelHook', it must implement "
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"TargetLowering::AdjustInstrPostInstrSelection!";
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#endif
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llvm_unreachable(0);
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}
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//===----------------------------------------------------------------------===//
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@ -1026,7 +1026,7 @@ multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
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}
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/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except it sets 's' bit by default.
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let isCodeGenOnly = 1, Defs = [CPSR] in {
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let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
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multiclass AsI1_rbin_s_is<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode, bit Commutable = 0> {
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@ -1090,7 +1090,7 @@ multiclass AsI1_rbin_s_is<bits<4> opcod, string opc,
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}
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/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
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let isCodeGenOnly = 1, Defs = [CPSR] in {
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let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
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multiclass AsI1_bin_s_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode, bit Commutable = 0> {
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@ -1278,7 +1278,7 @@ class AI_exta_rrot_np<bits<8> opcod, string opc>
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/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
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multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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string baseOpc, bit Commutable = 0> {
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let Defs = [CPSR], Uses = [CPSR] in {
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let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
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def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
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DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
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[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
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@ -1366,7 +1366,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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/// AI1_rsc_irs - Define instructions and patterns for rsc
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multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
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string baseOpc> {
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let Defs = [CPSR], Uses = [CPSR] in {
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let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
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def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
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DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
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[(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
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@ -592,7 +592,7 @@ multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
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/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
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/// instruction modifies the CPSR register.
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let isCodeGenOnly = 1, Defs = [CPSR] in {
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let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
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multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode, bit Commutable = 0> {
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@ -738,7 +738,7 @@ multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
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/// version is not needed since this is only for codegen.
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let isCodeGenOnly = 1, Defs = [CPSR] in {
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let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
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multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2sTwoRegImm<
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@ -1846,10 +1846,12 @@ defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
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IIC_iALUi, IIC_iALUr, IIC_iALUsi,
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BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
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let hasPostISelHook = 1 in {
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defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
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BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
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defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
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BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
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}
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// RSB
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defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
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@ -309,6 +309,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R) : TheDef(R), Operands(R) {
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isReMaterializable = R->getValueAsBit("isReMaterializable");
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hasDelaySlot = R->getValueAsBit("hasDelaySlot");
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usesCustomInserter = R->getValueAsBit("usesCustomInserter");
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hasPostISelHook = R->getValueAsBit("hasPostISelHook");
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hasCtrlDep = R->getValueAsBit("hasCtrlDep");
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isNotDuplicable = R->getValueAsBit("isNotDuplicable");
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hasSideEffects = R->getValueAsBit("hasSideEffects");
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@ -233,6 +233,7 @@ namespace llvm {
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bool isReMaterializable;
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bool hasDelaySlot;
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bool usesCustomInserter;
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bool hasPostISelHook;
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bool hasCtrlDep;
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bool isNotDuplicable;
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bool hasSideEffects;
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@ -288,6 +288,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)";
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if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
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if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
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if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)";
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if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
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if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)";
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if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)";
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@ -344,7 +345,7 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
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// We must emit the PHI opcode first...
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std::string Namespace = Target.getInstNamespace();
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if (Namespace.empty()) {
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fprintf(stderr, "No instructions defined!\n");
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exit(1);
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