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Avoid creating an extract element to an illegal type after LegalizeTypes has run.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149548 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang 2012-02-01 22:15:20 +00:00
parent ee498d3254
commit 845b1899b6
2 changed files with 30 additions and 2 deletions
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12
lib/Target/X86/X86ISelLowering.cpp
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@ -13604,6 +13604,7 @@ static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
/// when possible. /// when possible.
static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget *Subtarget) { const X86Subtarget *Subtarget) {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
if (N->getOpcode() == ISD::SHL) { if (N->getOpcode() == ISD::SHL) {
@ -13667,9 +13668,16 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
BaseShAmt = InVec.getOperand(1); BaseShAmt = InVec.getOperand(1);
} }
} }
if (BaseShAmt.getNode() == 0) if (BaseShAmt.getNode() == 0) {
// Don't create instructions with illegal types after legalize
// types has run.
if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
!DCI.isBeforeLegalize())
return SDValue();
BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
DAG.getIntPtrConstant(0)); DAG.getIntPtrConstant(0));
}
} else } else
return SDValue(); return SDValue();
@ -14833,7 +14841,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case ISD::MUL: return PerformMulCombine(N, DAG, DCI); case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
case ISD::SHL: case ISD::SHL:
case ISD::SRA: case ISD::SRA:
case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);

20
test/CodeGen/X86/shl-i64.ll Normal file
View File

@ -0,0 +1,20 @@
; RUN: llc -march=x86 < %s | FileCheck %s
; Make sure that we don't generate an illegal i64 extract after LegalizeType.
; CHECK: shll
define void @test_cl(<4 x i64>* %dst, <4 x i64>* %src, i32 %idx) {
entry:
%arrayidx = getelementptr inbounds <4 x i64> * %src, i32 %idx
%0 = load <4 x i64> * %arrayidx, align 32
%arrayidx1 = getelementptr inbounds <4 x i64> * %dst, i32 %idx
%1 = load <4 x i64> * %arrayidx1, align 32
%2 = extractelement <4 x i64> %1, i32 0
%and = and i64 %2, 63
%3 = insertelement <4 x i64> undef, i64 %and, i32 0
%splat = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> zeroinitializer
%shl = shl <4 x i64> %0, %splat
store <4 x i64> %shl, <4 x i64> * %arrayidx1, align 32
ret void
}