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[X86] Generalize CVTTPD2DQ/CVTTPD2UDQ and CVTDQ2PD/CVTUDQ2PD opcodes. NFCI
Replace the CVTTPD2DQ/CVTTPD2UDQ and CVTDQ2PD/CVTUDQ2PD opcodes with general versions. This is an initial step towards similar FP_TO_SINT/FP_TO_UINT and SINT_TO_FP/UINT_TO_FP lowering to AVX512 CVTTPS2QQ/CVTTPS2UQQ and CVTQQ2PS/CVTUQQ2PS with illegal types. Differential Revision: https://reviews.llvm.org/D27072 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287870 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -13844,7 +13844,7 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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if (SrcVT.isVector()) {
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if (SrcVT.isVector()) {
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if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
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if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
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return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
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return DAG.getNode(X86ISD::CVTSI2P, dl, VT,
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DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
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DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
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DAG.getUNDEF(SrcVT)));
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DAG.getUNDEF(SrcVT)));
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}
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}
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@ -14180,7 +14180,7 @@ SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
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llvm_unreachable("Custom UINT_TO_FP is not supported!");
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llvm_unreachable("Custom UINT_TO_FP is not supported!");
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case MVT::v2i32: {
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case MVT::v2i32: {
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if (VT == MVT::v2f64)
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if (VT == MVT::v2f64)
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return DAG.getNode(X86ISD::CVTUDQ2PD, dl, VT,
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return DAG.getNode(X86ISD::CVTUI2P, dl, VT,
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DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, N0,
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DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, N0,
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DAG.getUNDEF(SrcVT)));
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DAG.getUNDEF(SrcVT)));
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return SDValue();
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return SDValue();
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@ -22587,8 +22587,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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SDValue Src = N->getOperand(0);
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SDValue Src = N->getOperand(0);
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if (Src.getValueType() == MVT::v2f64) {
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if (Src.getValueType() == MVT::v2f64) {
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SDValue Idx = DAG.getIntPtrConstant(0, dl);
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SDValue Idx = DAG.getIntPtrConstant(0, dl);
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SDValue Res = DAG.getNode(IsSigned ? X86ISD::CVTTPD2DQ
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SDValue Res = DAG.getNode(IsSigned ? X86ISD::CVTTP2SI
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: X86ISD::CVTTPD2UDQ,
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: X86ISD::CVTTP2UI,
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dl, MVT::v4i32, Src);
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dl, MVT::v4i32, Src);
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Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i32, Res, Idx);
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Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i32, Res, Idx);
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Results.push_back(Res);
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Results.push_back(Res);
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@ -22926,10 +22926,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
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case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
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case X86ISD::VFPROUND_RND: return "X86ISD::VFPROUND_RND";
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case X86ISD::VFPROUND_RND: return "X86ISD::VFPROUND_RND";
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case X86ISD::VFPROUNDS_RND: return "X86ISD::VFPROUNDS_RND";
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case X86ISD::VFPROUNDS_RND: return "X86ISD::VFPROUNDS_RND";
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case X86ISD::CVTTPD2DQ: return "X86ISD::CVTTPD2DQ";
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case X86ISD::CVTTPD2UDQ: return "X86ISD::CVTTPD2UDQ";
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case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
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case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
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case X86ISD::CVT2MASK: return "X86ISD::CVT2MASK";
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case X86ISD::CVT2MASK: return "X86ISD::CVT2MASK";
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case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
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case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
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case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
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case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
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@ -23079,10 +23075,14 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::MULHRS: return "X86ISD::MULHRS";
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case X86ISD::MULHRS: return "X86ISD::MULHRS";
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case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
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case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
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case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
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case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
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case X86ISD::CVTTP2SI: return "X86ISD::CVTTP2SI";
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case X86ISD::CVTTP2UI: return "X86ISD::CVTTP2UI";
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case X86ISD::CVTTP2SI_RND: return "X86ISD::CVTTP2SI_RND";
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case X86ISD::CVTTP2SI_RND: return "X86ISD::CVTTP2SI_RND";
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case X86ISD::CVTTP2UI_RND: return "X86ISD::CVTTP2UI_RND";
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case X86ISD::CVTTP2UI_RND: return "X86ISD::CVTTP2UI_RND";
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case X86ISD::CVTTS2SI_RND: return "X86ISD::CVTTS2SI_RND";
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case X86ISD::CVTTS2SI_RND: return "X86ISD::CVTTS2SI_RND";
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case X86ISD::CVTTS2UI_RND: return "X86ISD::CVTTS2UI_RND";
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case X86ISD::CVTTS2UI_RND: return "X86ISD::CVTTS2UI_RND";
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case X86ISD::CVTSI2P: return "X86ISD::CVTSI2P";
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case X86ISD::CVTUI2P: return "X86ISD::CVTUI2P";
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case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
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case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
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case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
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case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
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case X86ISD::MULTISHIFT: return "X86ISD::MULTISHIFT";
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case X86ISD::MULTISHIFT: return "X86ISD::MULTISHIFT";
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@ -303,12 +303,6 @@ namespace llvm {
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// Vector FP round.
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// Vector FP round.
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VFPROUND, VFPROUND_RND, VFPROUNDS_RND,
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VFPROUND, VFPROUND_RND, VFPROUNDS_RND,
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// Vector double to signed/unsigned integer (truncated).
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CVTTPD2DQ, CVTTPD2UDQ,
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// Vector signed/unsigned integer to double.
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CVTDQ2PD, CVTUDQ2PD,
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// Convert a vector to mask, set bits base on MSB.
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// Convert a vector to mask, set bits base on MSB.
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CVT2MASK,
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CVT2MASK,
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@ -508,10 +502,13 @@ namespace llvm {
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CVTS2SI_RND, CVTS2UI_RND,
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CVTS2SI_RND, CVTS2UI_RND,
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// Vector float/double to signed/unsigned integer with truncation.
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// Vector float/double to signed/unsigned integer with truncation.
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CVTTP2SI_RND, CVTTP2UI_RND,
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CVTTP2SI, CVTTP2UI, CVTTP2SI_RND, CVTTP2UI_RND,
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// Scalar float/double to signed/unsigned integer with truncation.
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// Scalar float/double to signed/unsigned integer with truncation.
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CVTTS2SI_RND, CVTTS2UI_RND,
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CVTTS2SI_RND, CVTTS2UI_RND,
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// Vector signed/unsigned integer to float/double.
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CVTSI2P, CVTUI2P,
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// Save xmm argument registers to the stack, according to %al. An operator
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// Save xmm argument registers to the stack, according to %al. An operator
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// is needed so that this can be expanded with control flow.
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// is needed so that this can be expanded with control flow.
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VASTART_SAVE_XMM_REGS,
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VASTART_SAVE_XMM_REGS,
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@ -6391,8 +6391,8 @@ multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
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}
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}
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// Convert Signed/Unsigned Quardword to Float
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// Convert Signed/Unsigned Quardword to Float
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multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
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multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
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SDNode OpNode, SDNode OpNodeRnd> {
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SDNode OpNode128, SDNode OpNodeRnd> {
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let Predicates = [HasDQI] in {
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let Predicates = [HasDQI] in {
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
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avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
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avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
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@ -6403,7 +6403,7 @@ multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
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// memory forms of these instructions in Asm Parcer. They have the same
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// memory forms of these instructions in Asm Parcer. They have the same
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// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
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// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
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// due to the same reason.
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// due to the same reason.
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode128,
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"{1to2}", "{x}">, EVEX_V128;
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"{1to2}", "{x}">, EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
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"{1to4}", "{y}">, EVEX_V256;
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"{1to4}", "{y}">, EVEX_V256;
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@ -6419,7 +6419,7 @@ multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
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}
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}
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}
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}
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defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>,
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defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86VSintToFP>,
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XS, EVEX_CD8<32, CD8VH>;
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XS, EVEX_CD8<32, CD8VH>;
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defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
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defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
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@ -6430,7 +6430,7 @@ defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
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X86cvttp2siRnd>,
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X86cvttp2siRnd>,
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XS, EVEX_CD8<32, CD8VF>;
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XS, EVEX_CD8<32, CD8VF>;
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defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint, X86cvttpd2dq,
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defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint, X86cvttp2si,
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X86cvttp2siRnd>,
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X86cvttp2siRnd>,
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PD, VEX_W, EVEX_CD8<64, CD8VF>;
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PD, VEX_W, EVEX_CD8<64, CD8VF>;
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@ -6439,10 +6439,10 @@ defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
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EVEX_CD8<32, CD8VF>;
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EVEX_CD8<32, CD8VF>;
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defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
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defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
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X86cvttpd2udq, X86cvttp2uiRnd>, PS, VEX_W,
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X86cvttp2ui, X86cvttp2uiRnd>, PS, VEX_W,
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EVEX_CD8<64, CD8VF>;
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EVEX_CD8<64, CD8VF>;
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defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
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defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86VUintToFP>,
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XS, EVEX_CD8<32, CD8VH>;
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XS, EVEX_CD8<32, CD8VH>;
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defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
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defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
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@ -6497,10 +6497,10 @@ defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
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defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
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defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
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X86VUintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
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X86VUintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
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defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
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defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp, X86VSintToFP,
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X86VSintToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
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X86VSintToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
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defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
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defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp, X86VUintToFP,
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X86VUintToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
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X86VUintToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
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let Predicates = [HasAVX512, NoVLX] in {
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let Predicates = [HasAVX512, NoVLX] in {
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@ -6519,7 +6519,7 @@ def : Pat<(v4i32 (fp_to_uint (v4f64 VR256X:$src1))),
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(v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
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(v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
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VR256X:$src1, sub_ymm)))), sub_xmm)>;
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VR256X:$src1, sub_ymm)))), sub_xmm)>;
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def : Pat<(v4i32 (X86cvttpd2udq (v2f64 VR128X:$src))),
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def : Pat<(v4i32 (X86cvttp2ui (v2f64 VR128X:$src))),
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(EXTRACT_SUBREG (v8i32 (VCVTTPD2UDQZrr
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(EXTRACT_SUBREG (v8i32 (VCVTTPD2UDQZrr
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(v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
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(v8f64 (INSERT_SUBREG (IMPLICIT_DEF),
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VR128X:$src, sub_xmm)))), sub_xmm)>;
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VR128X:$src, sub_xmm)))), sub_xmm)>;
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@ -6539,7 +6539,7 @@ def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
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(v8i32 (INSERT_SUBREG (IMPLICIT_DEF),
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(v8i32 (INSERT_SUBREG (IMPLICIT_DEF),
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VR128X:$src1, sub_xmm)))), sub_ymm)>;
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VR128X:$src1, sub_xmm)))), sub_ymm)>;
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def : Pat<(v2f64 (X86cvtudq2pd (v4i32 VR128X:$src1))),
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def : Pat<(v2f64 (X86VUintToFP (v4i32 VR128X:$src1))),
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(EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
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(EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
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(v8i32 (INSERT_SUBREG (IMPLICIT_DEF),
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(v8i32 (INSERT_SUBREG (IMPLICIT_DEF),
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VR128X:$src1, sub_xmm)))), sub_xmm)>;
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VR128X:$src1, sub_xmm)))), sub_xmm)>;
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@ -6554,10 +6554,10 @@ let Predicates = [HasAVX512, HasVLX] in {
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(v4i32 (X86cvtp2UInt (v2f64 VR128X:$src)))))))),
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(v4i32 (X86cvtp2UInt (v2f64 VR128X:$src)))))))),
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(VCVTPD2UDQZ128rr VR128:$src)>;
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(VCVTPD2UDQZ128rr VR128:$src)>;
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def : Pat<(X86vzmovl (v2i64 (bitconvert
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def : Pat<(X86vzmovl (v2i64 (bitconvert
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(v4i32 (X86cvttpd2dq (v2f64 VR128X:$src)))))),
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(v4i32 (X86cvttp2si (v2f64 VR128X:$src)))))),
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(VCVTTPD2DQZ128rr VR128:$src)>;
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(VCVTTPD2DQZ128rr VR128:$src)>;
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def : Pat<(v4i32 (bitconvert (X86vzmovl (v2i64 (bitconvert
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def : Pat<(v4i32 (bitconvert (X86vzmovl (v2i64 (bitconvert
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(v4i32 (X86cvttpd2udq (v2f64 VR128X:$src)))))))),
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(v4i32 (X86cvttp2ui (v2f64 VR128X:$src)))))))),
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(VCVTTPD2UDQZ128rr VR128:$src)>;
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(VCVTTPD2UDQZ128rr VR128:$src)>;
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}
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}
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}
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}
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@ -67,18 +67,6 @@ def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
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def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
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def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
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def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
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def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
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def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
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def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
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def X86cvttpd2dq: SDNode<"X86ISD::CVTTPD2DQ",
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SDTypeProfile<1, 1, [SDTCisVT<0, v4i32>,
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|
||||||
SDTCisVT<1, v2f64>]>>;
|
|
||||||
def X86cvttpd2udq: SDNode<"X86ISD::CVTTPD2UDQ",
|
|
||||||
SDTypeProfile<1, 1, [SDTCisVT<0, v4i32>,
|
|
||||||
SDTCisVT<1, v2f64>]>>;
|
|
||||||
def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
|
|
||||||
SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
|
|
||||||
SDTCisVT<1, v4i32>]>>;
|
|
||||||
def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
|
|
||||||
SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
|
|
||||||
SDTCisVT<1, v4i32>]>>;
|
|
||||||
def X86pshufb : SDNode<"X86ISD::PSHUFB",
|
def X86pshufb : SDNode<"X86ISD::PSHUFB",
|
||||||
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
|
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
|
||||||
SDTCisSameAs<0,2>]>>;
|
SDTCisSameAs<0,2>]>>;
|
||||||
@ -513,12 +501,14 @@ def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
|
|||||||
|
|
||||||
def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
||||||
SDTCisInt<0>, SDTCisFP<1>]>;
|
SDTCisInt<0>, SDTCisFP<1>]>;
|
||||||
|
|
||||||
def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
||||||
SDTCisInt<0>, SDTCisFP<1>,
|
SDTCisInt<0>, SDTCisFP<1>,
|
||||||
SDTCisVT<2, i32>]>;
|
SDTCisVT<2, i32>]>;
|
||||||
def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
|
def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
|
||||||
SDTCisVec<1>, SDTCisVT<2, i32>]>;
|
SDTCisVec<1>, SDTCisVT<2, i32>]>;
|
||||||
|
|
||||||
|
def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
||||||
|
SDTCisFP<0>, SDTCisInt<1>]>;
|
||||||
def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
||||||
SDTCisFP<0>, SDTCisInt<1>,
|
SDTCisFP<0>, SDTCisInt<1>,
|
||||||
SDTCisVT<2, i32>]>;
|
SDTCisVT<2, i32>]>;
|
||||||
@ -547,6 +537,15 @@ def X86cvtp2IntRnd : SDNode<"X86ISD::CVTP2SI_RND", SDTFloatToIntRnd>;
|
|||||||
def X86cvtp2UIntRnd : SDNode<"X86ISD::CVTP2UI_RND", SDTFloatToIntRnd>;
|
def X86cvtp2UIntRnd : SDNode<"X86ISD::CVTP2UI_RND", SDTFloatToIntRnd>;
|
||||||
|
|
||||||
// Vector without rounding mode
|
// Vector without rounding mode
|
||||||
|
|
||||||
|
// cvtt fp-to-int staff
|
||||||
|
def X86cvttp2si : SDNode<"X86ISD::CVTTP2SI", SDTFloatToInt>;
|
||||||
|
def X86cvttp2ui : SDNode<"X86ISD::CVTTP2UI", SDTFloatToInt>;
|
||||||
|
|
||||||
|
def X86VSintToFP : SDNode<"X86ISD::CVTSI2P", SDTVintToFP>;
|
||||||
|
def X86VUintToFP : SDNode<"X86ISD::CVTUI2P", SDTVintToFP>;
|
||||||
|
|
||||||
|
// cvt int-to-fp staff
|
||||||
def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>;
|
def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>;
|
||||||
def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>;
|
def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>;
|
||||||
|
|
||||||
|
@ -2045,7 +2045,7 @@ let Predicates = [HasAVX, NoVLX] in
|
|||||||
def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||||
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
||||||
[(set VR128:$dst,
|
[(set VR128:$dst,
|
||||||
(v4i32 (X86cvttpd2dq (v2f64 VR128:$src))))],
|
(v4i32 (X86cvttp2si (v2f64 VR128:$src))))],
|
||||||
IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
|
IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
|
||||||
|
|
||||||
// The assembler can recognize rr 256-bit instructions by seeing a ymm
|
// The assembler can recognize rr 256-bit instructions by seeing a ymm
|
||||||
@ -2059,7 +2059,7 @@ let Predicates = [HasAVX, NoVLX] in
|
|||||||
def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||||
"cvttpd2dq{x}\t{$src, $dst|$dst, $src}",
|
"cvttpd2dq{x}\t{$src, $dst|$dst, $src}",
|
||||||
[(set VR128:$dst,
|
[(set VR128:$dst,
|
||||||
(v4i32 (X86cvttpd2dq (loadv2f64 addr:$src))))],
|
(v4i32 (X86cvttp2si (loadv2f64 addr:$src))))],
|
||||||
IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
|
IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
|
||||||
def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
|
def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
|
||||||
(VCVTTPD2DQrm VR128:$dst, f128mem:$src), 0>;
|
(VCVTTPD2DQrm VR128:$dst, f128mem:$src), 0>;
|
||||||
@ -2088,7 +2088,7 @@ let Predicates = [HasAVX, NoVLX] in {
|
|||||||
(v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))),
|
(v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))),
|
||||||
(VCVTPD2DQrr VR128:$src)>;
|
(VCVTPD2DQrr VR128:$src)>;
|
||||||
def : Pat<(X86vzmovl (v2i64 (bitconvert
|
def : Pat<(X86vzmovl (v2i64 (bitconvert
|
||||||
(v4i32 (X86cvttpd2dq (v2f64 VR128:$src)))))),
|
(v4i32 (X86cvttp2si (v2f64 VR128:$src)))))),
|
||||||
(VCVTTPD2DQrr VR128:$src)>;
|
(VCVTTPD2DQrr VR128:$src)>;
|
||||||
}
|
}
|
||||||
} // Predicates = [HasAVX]
|
} // Predicates = [HasAVX]
|
||||||
@ -2096,12 +2096,12 @@ let Predicates = [HasAVX, NoVLX] in {
|
|||||||
def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||||
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
||||||
[(set VR128:$dst,
|
[(set VR128:$dst,
|
||||||
(v4i32 (X86cvttpd2dq (v2f64 VR128:$src))))],
|
(v4i32 (X86cvttp2si (v2f64 VR128:$src))))],
|
||||||
IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
|
IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
|
||||||
def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
|
def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
|
||||||
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
||||||
[(set VR128:$dst,
|
[(set VR128:$dst,
|
||||||
(v4i32 (X86cvttpd2dq (memopv2f64 addr:$src))))],
|
(v4i32 (X86cvttp2si (memopv2f64 addr:$src))))],
|
||||||
IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
|
IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
|
||||||
|
|
||||||
let Predicates = [UseSSE2] in {
|
let Predicates = [UseSSE2] in {
|
||||||
@ -2110,7 +2110,7 @@ let Predicates = [UseSSE2] in {
|
|||||||
(v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))),
|
(v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))),
|
||||||
(CVTPD2DQrr VR128:$src)>;
|
(CVTPD2DQrr VR128:$src)>;
|
||||||
def : Pat<(X86vzmovl (v2i64 (bitconvert
|
def : Pat<(X86vzmovl (v2i64 (bitconvert
|
||||||
(v4i32 (X86cvttpd2dq (v2f64 VR128:$src)))))),
|
(v4i32 (X86cvttp2si (v2f64 VR128:$src)))))),
|
||||||
(CVTTPD2DQrr VR128:$src)>;
|
(CVTTPD2DQrr VR128:$src)>;
|
||||||
}
|
}
|
||||||
} // Predicates = [UseSSE2]
|
} // Predicates = [UseSSE2]
|
||||||
@ -2153,12 +2153,12 @@ let hasSideEffects = 0, mayLoad = 1 in
|
|||||||
def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
||||||
"vcvtdq2pd\t{$src, $dst|$dst, $src}",
|
"vcvtdq2pd\t{$src, $dst|$dst, $src}",
|
||||||
[(set VR128:$dst,
|
[(set VR128:$dst,
|
||||||
(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))))]>,
|
(v2f64 (X86VSintToFP (bc_v4i32 (loadv2i64 addr:$src)))))]>,
|
||||||
VEX, Sched<[WriteCvtI2FLd]>;
|
VEX, Sched<[WriteCvtI2FLd]>;
|
||||||
def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||||
"vcvtdq2pd\t{$src, $dst|$dst, $src}",
|
"vcvtdq2pd\t{$src, $dst|$dst, $src}",
|
||||||
[(set VR128:$dst,
|
[(set VR128:$dst,
|
||||||
(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))))]>,
|
(v2f64 (X86VSintToFP (v4i32 VR128:$src))))]>,
|
||||||
VEX, Sched<[WriteCvtI2F]>;
|
VEX, Sched<[WriteCvtI2F]>;
|
||||||
def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
|
def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
|
||||||
"vcvtdq2pd\t{$src, $dst|$dst, $src}",
|
"vcvtdq2pd\t{$src, $dst|$dst, $src}",
|
||||||
@ -2176,23 +2176,23 @@ let hasSideEffects = 0, mayLoad = 1 in
|
|||||||
def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
||||||
"cvtdq2pd\t{$src, $dst|$dst, $src}",
|
"cvtdq2pd\t{$src, $dst|$dst, $src}",
|
||||||
[(set VR128:$dst,
|
[(set VR128:$dst,
|
||||||
(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))))],
|
(v2f64 (X86VSintToFP (bc_v4i32 (loadv2i64 addr:$src)))))],
|
||||||
IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
|
IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
|
||||||
def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||||
"cvtdq2pd\t{$src, $dst|$dst, $src}",
|
"cvtdq2pd\t{$src, $dst|$dst, $src}",
|
||||||
[(set VR128:$dst,
|
[(set VR128:$dst,
|
||||||
(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))))],
|
(v2f64 (X86VSintToFP (v4i32 VR128:$src))))],
|
||||||
IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
|
IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
|
||||||
|
|
||||||
// AVX register conversion intrinsics
|
// AVX register conversion intrinsics
|
||||||
let Predicates = [HasAVX, NoVLX] in {
|
let Predicates = [HasAVX, NoVLX] in {
|
||||||
def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
|
def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
|
||||||
(VCVTDQ2PDrm addr:$src)>;
|
(VCVTDQ2PDrm addr:$src)>;
|
||||||
} // Predicates = [HasAVX, NoVLX]
|
} // Predicates = [HasAVX, NoVLX]
|
||||||
|
|
||||||
// SSE2 register conversion intrinsics
|
// SSE2 register conversion intrinsics
|
||||||
let Predicates = [UseSSE2] in {
|
let Predicates = [UseSSE2] in {
|
||||||
def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
|
def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
|
||||||
(CVTDQ2PDrm addr:$src)>;
|
(CVTDQ2PDrm addr:$src)>;
|
||||||
} // Predicates = [UseSSE2]
|
} // Predicates = [UseSSE2]
|
||||||
|
|
||||||
|
@ -561,7 +561,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
|||||||
X86_INTRINSIC_DATA(avx512_mask_cvtqq2pd_512, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvtqq2pd_512, INTR_TYPE_1OP_MASK,
|
||||||
ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND),
|
ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_128, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_128, INTR_TYPE_1OP_MASK,
|
||||||
ISD::SINT_TO_FP, 0),
|
X86ISD::CVTSI2P, 0),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_256, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_256, INTR_TYPE_1OP_MASK,
|
||||||
ISD::SINT_TO_FP, 0),
|
ISD::SINT_TO_FP, 0),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_512, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_512, INTR_TYPE_1OP_MASK,
|
||||||
@ -571,7 +571,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
|||||||
X86_INTRINSIC_DATA(avx512_mask_cvtss2sd_round, INTR_TYPE_SCALAR_MASK_RM,
|
X86_INTRINSIC_DATA(avx512_mask_cvtss2sd_round, INTR_TYPE_SCALAR_MASK_RM,
|
||||||
X86ISD::VFPEXTS_RND, 0),
|
X86ISD::VFPEXTS_RND, 0),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_128, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_128, INTR_TYPE_1OP_MASK,
|
||||||
X86ISD::CVTTPD2DQ, 0),
|
X86ISD::CVTTP2SI, 0),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_256, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_256, INTR_TYPE_1OP_MASK,
|
||||||
ISD::FP_TO_SINT, 0),
|
ISD::FP_TO_SINT, 0),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_512, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_512, INTR_TYPE_1OP_MASK,
|
||||||
@ -583,7 +583,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
|||||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2qq_512, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvttpd2qq_512, INTR_TYPE_1OP_MASK,
|
||||||
ISD::FP_TO_SINT, X86ISD::CVTTP2SI_RND),
|
ISD::FP_TO_SINT, X86ISD::CVTTP2SI_RND),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_128, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_128, INTR_TYPE_1OP_MASK,
|
||||||
X86ISD::CVTTPD2UDQ, 0),
|
X86ISD::CVTTP2UI, 0),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_256, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_256, INTR_TYPE_1OP_MASK,
|
||||||
ISD::FP_TO_UINT, 0),
|
ISD::FP_TO_UINT, 0),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_512, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_512, INTR_TYPE_1OP_MASK,
|
||||||
@ -631,7 +631,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
|||||||
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2pd_512, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2pd_512, INTR_TYPE_1OP_MASK,
|
||||||
ISD::UINT_TO_FP, X86ISD::UINT_TO_FP_RND),
|
ISD::UINT_TO_FP, X86ISD::UINT_TO_FP_RND),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_128, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_128, INTR_TYPE_1OP_MASK,
|
||||||
ISD::UINT_TO_FP, 0),
|
X86ISD::CVTUI2P, 0),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_256, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_256, INTR_TYPE_1OP_MASK,
|
||||||
ISD::UINT_TO_FP, 0),
|
ISD::UINT_TO_FP, 0),
|
||||||
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_512, INTR_TYPE_1OP_MASK,
|
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_512, INTR_TYPE_1OP_MASK,
|
||||||
@ -1612,7 +1612,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
|||||||
X86_INTRINSIC_DATA(sse2_cvtdq2ps, INTR_TYPE_1OP, ISD::SINT_TO_FP, 0),
|
X86_INTRINSIC_DATA(sse2_cvtdq2ps, INTR_TYPE_1OP, ISD::SINT_TO_FP, 0),
|
||||||
X86_INTRINSIC_DATA(sse2_cvtpd2dq, INTR_TYPE_1OP, X86ISD::CVTP2SI, 0),
|
X86_INTRINSIC_DATA(sse2_cvtpd2dq, INTR_TYPE_1OP, X86ISD::CVTP2SI, 0),
|
||||||
X86_INTRINSIC_DATA(sse2_cvtpd2ps, INTR_TYPE_1OP, X86ISD::VFPROUND, 0),
|
X86_INTRINSIC_DATA(sse2_cvtpd2ps, INTR_TYPE_1OP, X86ISD::VFPROUND, 0),
|
||||||
X86_INTRINSIC_DATA(sse2_cvttpd2dq, INTR_TYPE_1OP, X86ISD::CVTTPD2DQ, 0),
|
X86_INTRINSIC_DATA(sse2_cvttpd2dq, INTR_TYPE_1OP, X86ISD::CVTTP2SI, 0),
|
||||||
X86_INTRINSIC_DATA(sse2_cvttps2dq, INTR_TYPE_1OP, ISD::FP_TO_SINT, 0),
|
X86_INTRINSIC_DATA(sse2_cvttps2dq, INTR_TYPE_1OP, ISD::FP_TO_SINT, 0),
|
||||||
X86_INTRINSIC_DATA(sse2_max_pd, INTR_TYPE_2OP, X86ISD::FMAX, 0),
|
X86_INTRINSIC_DATA(sse2_max_pd, INTR_TYPE_2OP, X86ISD::FMAX, 0),
|
||||||
X86_INTRINSIC_DATA(sse2_min_pd, INTR_TYPE_2OP, X86ISD::FMIN, 0),
|
X86_INTRINSIC_DATA(sse2_min_pd, INTR_TYPE_2OP, X86ISD::FMIN, 0),
|
||||||
|
Loading…
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Reference in New Issue
Block a user