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This patch changes the ownership of TLOF from TargetLoweringBase to TargetMachine so that different subtargets could share the TLOF effectively

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221878 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Aditya Nandakumar 2014-11-13 09:26:31 +00:00
parent db1e51359d
commit 847729d19a
39 changed files with 142 additions and 65 deletions
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4
include/llvm/Target/TargetLowering.h
View File

@ -137,10 +137,10 @@ public:
llvm_unreachable("Invalid content kind");
}
/// NOTE: The constructor takes ownership of TLOF.
/// NOTE: The TargetMachine owns TLOF.
explicit TargetLoweringBase(const TargetMachine &TM,
const TargetLoweringObjectFile *TLOF);
virtual ~TargetLoweringBase();
virtual ~TargetLoweringBase() {}
protected:
/// \brief Initialize all of the actions to default values.

4
include/llvm/Target/TargetMachine.h
View File

@ -44,6 +44,7 @@ class ScalarTargetTransformInfo;
class VectorTargetTransformInfo;
class formatted_raw_ostream;
class raw_ostream;
class TargetLoweringObjectFile;
// The old pass manager infrastructure is hidden in a legacy namespace now.
namespace legacy {
@ -102,6 +103,9 @@ public:
virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const {
return getSubtargetImpl();
}
virtual TargetLoweringObjectFile *getObjFileLowering() const {
return nullptr;
}
/// getSubtarget - This method returns a pointer to the specified type of
/// TargetSubtargetInfo. In debug builds, it verifies that the object being

4
lib/CodeGen/TargetLoweringBase.cpp
View File

@ -737,10 +737,6 @@ TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
InitLibcallCallingConvs(LibcallCallingConvs);
}
TargetLoweringBase::~TargetLoweringBase() {
delete &TLOF;
}
void TargetLoweringBase::initActions() {
// All operations default to being supported.
memset(OpActions, 0, sizeof(OpActions));

11
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -66,18 +66,9 @@ EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
cl::desc("Allow AArch64 SLI/SRI formation"),
cl::init(false));
//===----------------------------------------------------------------------===//
// AArch64 Lowering public interface.
//===----------------------------------------------------------------------===//
static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
if (TT.isOSBinFormatMachO())
return new AArch64_MachoTargetObjectFile();
return new AArch64_ELFTargetObjectFile();
}
AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM)
: TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
: TargetLowering(TM, TM.getObjFileLowering()) {
Subtarget = &TM.getSubtarget<AArch64Subtarget>();
// AArch64 doesn't have comparisons which set GPRs or setcc instructions, so

12
lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -12,6 +12,7 @@
#include "AArch64.h"
#include "AArch64TargetMachine.h"
#include "AArch64TargetObjectFile.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/IR/Function.h"
@ -87,6 +88,16 @@ extern "C" void LLVMInitializeAArch64Target() {
RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
}
//===----------------------------------------------------------------------===//
// AArch64 Lowering public interface.
//===----------------------------------------------------------------------===//
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
if (TT.isOSBinFormatMachO())
return make_unique<AArch64_MachoTargetObjectFile>();
return make_unique<AArch64_ELFTargetObjectFile>();
}
/// TargetMachine ctor - Create an AArch64 architecture model.
///
AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
@ -96,6 +107,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OL,
bool LittleEndian)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) {
initAsmInfo();
}

5
lib/Target/AArch64/AArch64TargetMachine.h
View File

@ -23,6 +23,7 @@ namespace llvm {
class AArch64TargetMachine : public LLVMTargetMachine {
protected:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
AArch64Subtarget Subtarget;
mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
@ -43,6 +44,10 @@ public:
/// \brief Register AArch64 analysis passes with a pass manager.
void addAnalysisPasses(PassManagerBase &PM) override;
TargetLoweringObjectFile* getObjFileLowering() const override {
return TLOF.get();
}
private:
bool isLittle;
};

10
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -156,16 +156,8 @@ void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
}
static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
if (TT.isOSBinFormatMachO())
return new TargetLoweringObjectFileMachO();
if (TT.isOSWindows())
return new TargetLoweringObjectFileCOFF();
return new ARMElfTargetObjectFile();
}
ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM)
: TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
: TargetLowering(TM, TM.getObjFileLowering()) {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
RegInfo = TM.getSubtargetImpl()->getRegisterInfo();
Itins = TM.getSubtargetImpl()->getInstrItineraryData();

10
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -13,6 +13,7 @@
#include "ARM.h"
#include "ARMTargetMachine.h"
#include "ARMFrameLowering.h"
#include "ARMTargetObjectFile.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCAsmInfo.h"
@ -43,6 +44,14 @@ extern "C" void LLVMInitializeARMTarget() {
RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
}
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
if (TT.isOSBinFormatMachO())
return make_unique<TargetLoweringObjectFileMachO>();
if (TT.isOSWindows())
return make_unique<TargetLoweringObjectFileCOFF>();
return make_unique<ARMElfTargetObjectFile>();
}
/// TargetMachine ctor - Create an ARM architecture model.
///
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
@ -51,6 +60,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
// Default to triple-appropriate float ABI

5
lib/Target/ARM/ARMTargetMachine.h
View File

@ -23,6 +23,7 @@ namespace llvm {
class ARMBaseTargetMachine : public LLVMTargetMachine {
protected:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
ARMSubtarget Subtarget;
bool isLittle;
mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
@ -43,6 +44,10 @@ public:
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
};
/// ARMTargetMachine - ARM target machine.

2
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -1043,7 +1043,7 @@ HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
//===----------------------------------------------------------------------===//
HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
: TargetLowering(targetmachine, new HexagonTargetObjectFile()),
: TargetLowering(targetmachine, targetmachine.getObjFileLowering()),
TM(targetmachine) {
const HexagonSubtarget &Subtarget = TM.getSubtarget<HexagonSubtarget>();

1
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -70,6 +70,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<HexagonTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}

5
lib/Target/Hexagon/HexagonTargetMachine.h
View File

@ -23,6 +23,7 @@ namespace llvm {
class Module;
class HexagonTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
HexagonSubtarget Subtarget;
public:
@ -37,6 +38,10 @@ public:
static unsigned getModuleMatchQuality(const Module &M);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
};
extern bool flag_aligned_memcpy;

2
lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -58,7 +58,7 @@ HWMultMode("msp430-hwmult-mode", cl::Hidden,
clEnumValEnd));
MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM)
: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
: TargetLowering(TM, TM.getObjFileLowering()) {
// Set up the register classes.
addRegisterClass(MVT::i8, &MSP430::GR8RegClass);

2
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "MSP430TargetMachine.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "MSP430.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/MC/MCAsmInfo.h"
@ -30,6 +31,7 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}

5
lib/Target/MSP430/MSP430TargetMachine.h
View File

@ -24,6 +24,7 @@ namespace llvm {
/// MSP430TargetMachine
///
class MSP430TargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
MSP430Subtarget Subtarget;
public:
@ -36,6 +37,10 @@ public:
return &Subtarget;
}
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
}; // MSP430TargetMachine.
} // end namespace llvm

2
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -203,7 +203,7 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI)
: TargetLowering(TM, new MipsTargetObjectFile()), Subtarget(STI) {
: TargetLowering(TM, TM.getObjFileLowering()), Subtarget(STI) {
// Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...).
setBooleanContents(ZeroOrOneBooleanContent);

5
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -26,6 +26,7 @@
#include "MipsSEISelDAGToDAG.h"
#include "MipsSEISelLowering.h"
#include "MipsSEInstrInfo.h"
#include "MipsTargetObjectFile.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/PassManager.h"
@ -56,7 +57,9 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
isLittle(isLittle), Subtarget(nullptr),
isLittle(isLittle),
TLOF(make_unique<MipsTargetObjectFile>()),
Subtarget(nullptr),
DefaultSubtarget(TT, CPU, FS, isLittle, this),
NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
isLittle, this),

7
lib/Target/Mips/MipsTargetMachine.h
View File

@ -26,6 +26,7 @@ class MipsRegisterInfo;
class MipsTargetMachine : public LLVMTargetMachine {
bool isLittle;
std::unique_ptr<TargetLoweringObjectFile> TLOF;
MipsSubtarget *Subtarget;
MipsSubtarget DefaultSubtarget;
MipsSubtarget NoMips16Subtarget;
@ -38,8 +39,6 @@ public:
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
virtual ~MipsTargetMachine() {}
void addAnalysisPasses(PassManagerBase &PM) override;
const MipsSubtarget *getSubtargetImpl() const override {
@ -55,6 +54,10 @@ public:
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
};
/// MipsebTargetMachine - Mips32/64 big endian target machine.

2
lib/Target/NVPTX/NVPTXISelLowering.cpp
View File

@ -107,7 +107,7 @@ static void ComputePTXValueVTs(const TargetLowering &TLI, Type *Ty,
// NVPTXTargetLowering Constructor.
NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM)
: TargetLowering(TM, new NVPTXTargetObjectFile()), nvTM(&TM),
: TargetLowering(TM, TM.getObjFileLowering()), nvTM(&TM),
nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
// always lower memset, memcpy, and memmove intrinsics to load/store

2
lib/Target/NVPTX/NVPTXTargetMachine.cpp
View File

@ -16,6 +16,7 @@
#include "NVPTX.h"
#include "NVPTXAllocaHoisting.h"
#include "NVPTXLowerAggrCopies.h"
#include "NVPTXTargetObjectFile.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
@ -74,6 +75,7 @@ NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<NVPTXTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this, is64bit) {
initAsmInfo();
}

4
lib/Target/NVPTX/NVPTXTargetMachine.h
View File

@ -25,6 +25,7 @@ namespace llvm {
/// NVPTXTargetMachine
///
class NVPTXTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
NVPTXSubtarget Subtarget;
// Hold Strings that can be free'd all together with NVPTXTargetMachine
@ -48,6 +49,9 @@ public:
bool = true) override {
return true;
}
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
/// \brief Register NVPTX analysis passes with a pass manager.
void addAnalysisPasses(PassManagerBase &PM) override;

11
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -55,17 +55,8 @@ cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
// FIXME: Remove this once the bug has been fixed!
extern cl::opt<bool> ANDIGlueBug;
static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
// If it isn't a Mach-O file then it's going to be a linux ELF
// object file.
if (TT.isOSDarwin())
return new TargetLoweringObjectFileMachO();
return new PPC64LinuxTargetObjectFile();
}
PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM)
: TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
: TargetLowering(TM, TM.getObjFileLowering()),
Subtarget(*TM.getSubtargetImpl()) {
setPow2SDivIsCheap();

11
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "PPCTargetMachine.h"
#include "PPCTargetObjectFile.h"
#include "PPC.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Function.h"
@ -60,6 +61,15 @@ static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, String
return FullFS;
}
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
// If it isn't a Mach-O file then it's going to be a linux ELF
// object file.
if (TT.isOSDarwin())
return make_unique<TargetLoweringObjectFileMachO>();
return make_unique<PPC64LinuxTargetObjectFile>();
}
// The FeatureString here is a little subtle. We are modifying the feature string
// with what are (currently) non-function specific overrides as it goes into the
// LLVMTargetMachine constructor and then using the stored value in the
@ -70,6 +80,7 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(TT, CPU, TargetFS, *this) {
initAsmInfo();
}

4
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -24,6 +24,7 @@ namespace llvm {
/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
///
class PPCTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
PPCSubtarget Subtarget;
mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
@ -42,6 +43,9 @@ public:
/// \brief Register PPC analysis passes with a pass manager.
void addAnalysisPasses(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
};
/// PPC32TargetMachine - PowerPC 32-bit target machine.

2
lib/Target/R600/AMDGPUISelLowering.cpp
View File

@ -103,7 +103,7 @@ EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
}
AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
TargetLowering(TM, new TargetLoweringObjectFileELF()) {
TargetLowering(TM, TM.getObjFileLowering()) {
Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();

3
lib/Target/R600/AMDGPUTargetMachine.cpp
View File

@ -22,6 +22,7 @@
#include "SIInstrInfo.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Verifier.h"
@ -54,12 +55,14 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
CodeModel::Model CM,
CodeGenOpt::Level OptLevel)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
TLOF(new TargetLoweringObjectFileELF()),
Subtarget(TT, CPU, FS, *this), IntrinsicInfo() {
setRequiresStructuredCFG(true);
initAsmInfo();
}
AMDGPUTargetMachine::~AMDGPUTargetMachine() {
delete TLOF;
}
namespace {

4
lib/Target/R600/AMDGPUTargetMachine.h
View File

@ -25,6 +25,7 @@
namespace llvm {
class AMDGPUTargetMachine : public LLVMTargetMachine {
TargetLoweringObjectFile *TLOF;
AMDGPUSubtarget Subtarget;
AMDGPUIntrinsicInfo IntrinsicInfo;
@ -43,6 +44,9 @@ public:
/// \brief Register R600 analysis passes with a pass manager.
void addAnalysisPasses(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF;
}
};
} // End namespace llvm

2
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -1366,7 +1366,7 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
}
SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
: TargetLowering(TM, new SparcELFTargetObjectFile()) {
: TargetLowering(TM, TM.getObjFileLowering()) {
Subtarget = &TM.getSubtarget<SparcSubtarget>();
// Set up the register classes.

2
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "SparcTargetMachine.h"
#include "SparcTargetObjectFile.h"
#include "Sparc.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/PassManager.h"
@ -32,6 +33,7 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OL,
bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<SparcELFTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this, is64bit) {
initAsmInfo();
}

4
lib/Target/Sparc/SparcTargetMachine.h
View File

@ -21,6 +21,7 @@
namespace llvm {
class SparcTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
SparcSubtarget Subtarget;
public:
SparcTargetMachine(const Target &T, StringRef TT,
@ -32,6 +33,9 @@ public:
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
};
/// SparcV8TargetMachine - Sparc 32-bit target machine

2
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -81,7 +81,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) {
}
SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm)
: TargetLowering(tm, new TargetLoweringObjectFileELF()),
: TargetLowering(tm, tm.getObjFileLowering()),
Subtarget(tm.getSubtarget<SystemZSubtarget>()) {
MVT PtrVT = getPointerTy();

2
lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@ -11,6 +11,7 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
using namespace llvm;
@ -25,6 +26,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}

4
lib/Target/SystemZ/SystemZTargetMachine.h
View File

@ -23,6 +23,7 @@ namespace llvm {
class TargetFrameLowering;
class SystemZTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
SystemZSubtarget Subtarget;
public:
@ -37,6 +38,9 @@ public:
}
// Override LLVMTargetMachine
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
};
} // end namespace llvm

20
lib/Target/X86/X86ISelLowering.cpp
View File

@ -199,28 +199,10 @@ static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
}
static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
if (TT.isOSBinFormatMachO()) {
if (TT.getArch() == Triple::x86_64)
return new X86_64MachoTargetObjectFile();
return new TargetLoweringObjectFileMachO();
}
if (TT.isOSLinux())
return new X86LinuxTargetObjectFile();
if (TT.isOSBinFormatELF())
return new TargetLoweringObjectFileELF();
if (TT.isKnownWindowsMSVCEnvironment())
return new X86WindowsTargetObjectFile();
if (TT.isOSBinFormatCOFF())
return new TargetLoweringObjectFileCOFF();
llvm_unreachable("unknown subtarget type");
}
// FIXME: This should stop caching the target machine as soon as
// we can remove resetOperationActions et al.
X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
: TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
: TargetLowering(TM, TM.getObjFileLowering()) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
X86ScalarSSEf64 = Subtarget->hasSSE2();
X86ScalarSSEf32 = Subtarget->hasSSE1();

20
lib/Target/X86/X86TargetMachine.cpp
View File

@ -13,6 +13,7 @@
#include "X86TargetMachine.h"
#include "X86.h"
#include "X86TargetObjectFile.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Function.h"
#include "llvm/PassManager.h"
@ -30,6 +31,24 @@ extern "C" void LLVMInitializeX86Target() {
void X86TargetMachine::anchor() { }
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
if (TT.isOSBinFormatMachO()) {
if (TT.getArch() == Triple::x86_64)
return make_unique<X86_64MachoTargetObjectFile>();
return make_unique<TargetLoweringObjectFileMachO>();
}
if (TT.isOSLinux())
return make_unique<X86LinuxTargetObjectFile>();
if (TT.isOSBinFormatELF())
return make_unique<TargetLoweringObjectFileELF>();
if (TT.isKnownWindowsMSVCEnvironment())
return make_unique<X86WindowsTargetObjectFile>();
if (TT.isOSBinFormatCOFF())
return make_unique<TargetLoweringObjectFileCOFF>();
llvm_unreachable("unknown subtarget type");
}
/// X86TargetMachine ctor - Create an X86 target.
///
X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
@ -37,6 +56,7 @@ X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
// default to hard float ABI
if (Options.FloatABIType == FloatABI::Default)

4
lib/Target/X86/X86TargetMachine.h
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@ -24,6 +24,7 @@ class StringRef;
class X86TargetMachine final : public LLVMTargetMachine {
virtual void anchor();
std::unique_ptr<TargetLoweringObjectFile> TLOF;
X86Subtarget Subtarget;
mutable StringMap<std::unique_ptr<X86Subtarget>> SubtargetMap;
@ -41,6 +42,9 @@ public:
// Set up the pass pipeline.
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
};
} // End llvm namespace

2
lib/Target/XCore/XCoreISelLowering.cpp
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@ -69,7 +69,7 @@ getTargetNodeName(unsigned Opcode) const
}
XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM)
: TargetLowering(TM, new XCoreTargetObjectFile()), TM(TM),
: TargetLowering(TM, TM.getObjFileLowering()), TM(TM),
Subtarget(TM.getSubtarget<XCoreSubtarget>()) {
// Set up the register classes.

2
lib/Target/XCore/XCoreTargetMachine.cpp
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@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "XCoreTargetMachine.h"
#include "XCoreTargetObjectFile.h"
#include "XCore.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Module.h"
@ -26,6 +27,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<XCoreTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}

4
lib/Target/XCore/XCoreTargetMachine.h
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@ -20,6 +20,7 @@
namespace llvm {
class XCoreTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
XCoreSubtarget Subtarget;
public:
XCoreTargetMachine(const Target &T, StringRef TT,
@ -33,6 +34,9 @@ public:
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
void addAnalysisPasses(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
};
} // end namespace llvm