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LegalizeDAG: Support promoting [US]DIV and [US]REM operations

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Summary:
AMDGPU will need this one i16 is added as a legal type.  This is tested by:

test/CodeGen/AMDGPU/sdiv.ll
test/CodeGen/AMDGPU/sdivrem24.ll
test/CodeGen/AMDGPU/udiv.ll
test/CodeGen/AMDGPU/udivrem24.ll

Reviewers: bogner, efriedma

Subscribers: efriedma, wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D25699

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285199 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2016-10-26 14:52:25 +00:00
parent 1a633d108a
commit 84b175c135
1 changed files with 18 additions and 1 deletions
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19
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -4148,6 +4148,10 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
ReplacedNode(Node);
break;
}
case ISD::SDIV:
case ISD::SREM:
case ISD::UDIV:
case ISD::UREM:
case ISD::AND:
case ISD::OR:
case ISD::XOR: {
@ -4157,7 +4161,20 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
TruncOp = ISD::BITCAST;
} else {
assert(OVT.isInteger() && "Cannot promote logic operation");
ExtOp = ISD::ANY_EXTEND;
switch (Node->getOpcode()) {
default:
ExtOp = ISD::ANY_EXTEND;
break;
case ISD::SDIV:
case ISD::SREM:
ExtOp = ISD::SIGN_EXTEND;
break;
case ISD::UDIV:
case ISD::UREM:
ExtOp = ISD::ZERO_EXTEND;
break;
}
TruncOp = ISD::TRUNCATE;
}
// Promote each of the values to the new type.