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Add initial support for decoding NEON instructions in Thumb2 mode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-10 19:01:10 +00:00
parent 0d886401b3
commit 8533ebad6f
3 changed files with 59 additions and 4 deletions
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6
lib/Target/ARM/ARMInstrFormats.td
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@ -1608,7 +1608,7 @@ class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
let Pattern = pattern;
list<Predicate> Predicates = [HasNEON];
let DecoderNamespace = "NEON";
let DecoderNamespace = "NEONData";
}
// Same as NeonI except it does not have a "data type" specifier.
@ -1621,7 +1621,7 @@ class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
let AsmString = !strconcat(opc, "${p}", "\t", asm);
let Pattern = pattern;
list<Predicate> Predicates = [HasNEON];
let DecoderNamespace = "NEON";
let DecoderNamespace = "NEONData";
}
class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
@ -1636,6 +1636,7 @@ class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
let Inst{7-4} = op7_4;
let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
let DecoderNamespace = "NEONLoadStore";
bits<5> Vd;
bits<6> Rn;
@ -1911,6 +1912,7 @@ class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
list<Predicate> Predicates = [HasNEON];
let PostEncoderMethod = "NEONThumb2DupPostEncoder";
let DecoderNamespace = "NEONDup";
bits<5> V;
bits<4> R;

54
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -249,12 +249,32 @@ bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
}
MI.clear();
result = decodeNEONInstruction32(MI, insn, Address, this);
result = decodeNEONDataInstruction32(MI, insn, Address, this);
if (result) {
Size = 4;
// Add a fake predicate operand, because we share these instruction
// definitions with Thumb2 where these instructions are predicable.
if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
return true;
}
MI.clear();
result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
if (result) {
Size = 4;
// Add a fake predicate operand, because we share these instruction
// definitions with Thumb2 where these instructions are predicable.
if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
return true;
}
MI.clear();
result = decodeNEONDupInstruction32(MI, insn, Address, this);
if (result) {
Size = 4;
// Add a fake predicate operand, because we share these instruction
// definitions with Thumb2 where these instructions are predicable.
if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
return true;
}
@ -433,6 +453,14 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
return true;
}
MI.clear();
result = decodeCommonInstruction32(MI, insn32, Address, this);
if (result) {
Size = 4;
AddThumbPredicate(MI);
return true;
}
MI.clear();
result = decodeVFPInstruction32(MI, insn32, Address, this);
if (result) {
@ -442,7 +470,29 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
}
MI.clear();
result = decodeCommonInstruction32(MI, insn32, Address, this);
if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
uint32_t NEONDataInsn = insn32;
NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
NEONDataInsn |= 0x12000000; // Set bits 28 and 25
result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
if (result) {
Size = 4;
AddThumbPredicate(MI);
return true;
}
}
MI.clear();
result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this);
if (result) {
Size = 4;
AddThumbPredicate(MI);
return true;
}
MI.clear();
result = decodeNEONDupInstruction32(MI, insn32, Address, this);
if (result) {
Size = 4;
AddThumbPredicate(MI);

3
test/MC/Disassembler/ARM/thumb-tests.txt
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@ -265,3 +265,6 @@
# CHECK: bne #24
0x0c 0xd1
# CHECK: vadd.f32 q0, q1, q2
0x02 0xef 0x44 0x0d