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[ARM] GlobalISel: Select s64 G_FCMP
Very similar to how we select s32 G_FCMP, the only thing that is different is the exact opcodes that we use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307763 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Diana Picus
parent
fbec1c990e
commit
8577619105
@ -348,6 +348,9 @@ template <typename T> struct ARMInstructionSelector::CmpHelper {
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// The assumed register bank ID for the operands.
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static const unsigned OperandRegBankID;
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// The assumed size in bits for the operands.
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static const unsigned OperandSize;
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// The assumed register bank ID for the result.
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static const unsigned ResultRegBankID = ARM::GPRRegBankID;
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@ -420,7 +423,7 @@ private:
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bool validateOpReg(unsigned OpReg, MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) {
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if (MRI.getType(OpReg).getSizeInBits() != 32) {
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if (MRI.getType(OpReg).getSizeInBits() != OperandSize) {
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DEBUG(dbgs() << "Unsupported size for comparison operand");
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return false;
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}
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@ -452,6 +455,9 @@ const unsigned ARMInstructionSelector::CmpHelper<int>::ComparisonOpcode =
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<float>::ComparisonOpcode =
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ARM::VCMPS;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<double>::ComparisonOpcode =
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ARM::VCMPD;
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// Specialize the opcode to be used for reading the comparison flags for
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// different types of operands.
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@ -461,6 +467,9 @@ const unsigned ARMInstructionSelector::CmpHelper<int>::ReadFlagsOpcode =
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<float>::ReadFlagsOpcode =
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ARM::FMSTAT;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<double>::ReadFlagsOpcode =
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ARM::FMSTAT;
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// Specialize the register bank where the operands of the comparison are assumed
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// to live.
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@ -470,6 +479,17 @@ const unsigned ARMInstructionSelector::CmpHelper<int>::OperandRegBankID =
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<float>::OperandRegBankID =
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ARM::FPRRegBankID;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<double>::OperandRegBankID =
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ARM::FPRRegBankID;
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// Specialize the size that the operands of the comparison are assumed to have.
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<int>::OperandSize = 32;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<float>::OperandSize = 32;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<double>::OperandSize = 64;
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template <typename T>
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bool ARMInstructionSelector::selectCmp(MachineInstrBuilder &MIB,
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@ -667,9 +687,24 @@ bool ARMInstructionSelector::select(MachineInstr &I) const {
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return selectSelect(MIB, TII, MRI, TRI, RBI);
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case G_ICMP:
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return selectCmp<int>(MIB, TII, MRI, TRI, RBI);
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case G_FCMP:
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case G_FCMP: {
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assert(TII.getSubtarget().hasVFP2() && "Can't select fcmp without VFP");
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return selectCmp<float>(MIB, TII, MRI, TRI, RBI);
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unsigned OpReg = I.getOperand(2).getReg();
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unsigned Size = MRI.getType(OpReg).getSizeInBits();
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if (Size == 32)
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return selectCmp<float>(MIB, TII, MRI, TRI, RBI);
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if (Size == 64) {
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if (TII.getSubtarget().isFPOnlySP()) {
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DEBUG(dbgs() << "Subtarget only supports single precision");
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return false;
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}
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return selectCmp<double>(MIB, TII, MRI, TRI, RBI);
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}
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DEBUG(dbgs() << "Unsupported size for G_FCMP operand");
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return false;
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}
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case G_GEP:
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I.setDesc(TII.get(ARM::ADDrr));
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MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
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@ -30,6 +30,25 @@
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define void @test_fcmp_one_s32() #0 { ret void }
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define void @test_fcmp_ueq_s32() #0 { ret void }
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define void @test_fcmp_true_s64() #0 { ret void }
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define void @test_fcmp_false_s64() #0 { ret void }
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define void @test_fcmp_oeq_s64() #0 { ret void }
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define void @test_fcmp_ogt_s64() #0 { ret void }
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define void @test_fcmp_oge_s64() #0 { ret void }
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define void @test_fcmp_olt_s64() #0 { ret void }
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define void @test_fcmp_ole_s64() #0 { ret void }
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define void @test_fcmp_ord_s64() #0 { ret void }
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define void @test_fcmp_ugt_s64() #0 { ret void }
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define void @test_fcmp_uge_s64() #0 { ret void }
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define void @test_fcmp_ult_s64() #0 { ret void }
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define void @test_fcmp_ule_s64() #0 { ret void }
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define void @test_fcmp_une_s64() #0 { ret void }
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define void @test_fcmp_uno_s64() #0 { ret void }
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define void @test_fcmp_one_s64() #0 { ret void }
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define void @test_fcmp_ueq_s64() #0 { ret void }
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attributes #0 = { "target-features"="+vfp2" }
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...
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---
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@ -978,3 +997,589 @@ body: |
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_fcmp_true_s64
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# CHECK-LABEL: name: test_fcmp_true_s64
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: fprb }
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- { id: 1, class: fprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: %d0, %d1
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%0(s64) = COPY %d0
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%1(s64) = COPY %d1
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%2(s1) = G_FCMP floatpred(true), %0(s64), %1
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; CHECK: [[RES:%[0-9]+]] = MOVi 1, 14, _, _
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%3(s32) = G_ZEXT %2(s1)
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; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
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%r0 = COPY %3(s32)
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; CHECK: %r0 = COPY [[RET]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_fcmp_false_s64
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# CHECK-LABEL: name: test_fcmp_false_s64
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: fprb }
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- { id: 1, class: fprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: %d0, %d1
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%0(s64) = COPY %d0
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%1(s64) = COPY %d1
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%2(s1) = G_FCMP floatpred(false), %0(s64), %1
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; CHECK: [[RES:%[0-9]+]] = MOVi 0, 14, _, _
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%3(s32) = G_ZEXT %2(s1)
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; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
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%r0 = COPY %3(s32)
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; CHECK: %r0 = COPY [[RET]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_fcmp_oeq_s64
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# CHECK-LABEL: name: test_fcmp_oeq_s64
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: fprb }
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- { id: 1, class: fprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: %d0, %d1
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%0(s64) = COPY %d0
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; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
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%1(s64) = COPY %d1
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; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
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%2(s1) = G_FCMP floatpred(oeq), %0(s64), %1
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; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
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; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
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; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
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; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
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%3(s32) = G_ZEXT %2(s1)
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; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
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%r0 = COPY %3(s32)
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; CHECK: %r0 = COPY [[RET]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_fcmp_ogt_s64
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# CHECK-LABEL: name: test_fcmp_ogt_s64
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: fprb }
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- { id: 1, class: fprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: %d0, %d1
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%0(s64) = COPY %d0
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; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
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%1(s64) = COPY %d1
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; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
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%2(s1) = G_FCMP floatpred(ogt), %0(s64), %1
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; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
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; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
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; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
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; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
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%3(s32) = G_ZEXT %2(s1)
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; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
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%r0 = COPY %3(s32)
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; CHECK: %r0 = COPY [[RET]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_fcmp_oge_s64
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# CHECK-LABEL: name: test_fcmp_oge_s64
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: fprb }
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- { id: 1, class: fprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: %d0, %d1
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%0(s64) = COPY %d0
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; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
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%1(s64) = COPY %d1
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; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
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%2(s1) = G_FCMP floatpred(oge), %0(s64), %1
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; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
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; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
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; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
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; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
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%3(s32) = G_ZEXT %2(s1)
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; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
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%r0 = COPY %3(s32)
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; CHECK: %r0 = COPY [[RET]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_fcmp_olt_s64
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# CHECK-LABEL: name: test_fcmp_olt_s64
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: fprb }
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- { id: 1, class: fprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: %d0, %d1
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%0(s64) = COPY %d0
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; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
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%1(s64) = COPY %d1
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; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
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%2(s1) = G_FCMP floatpred(olt), %0(s64), %1
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; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
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; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
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; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
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; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 4, %cpsr
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%3(s32) = G_ZEXT %2(s1)
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; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
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%r0 = COPY %3(s32)
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; CHECK: %r0 = COPY [[RET]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_fcmp_ole_s64
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# CHECK-LABEL: name: test_fcmp_ole_s64
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: fprb }
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- { id: 1, class: fprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: %d0, %d1
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%0(s64) = COPY %d0
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; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
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%1(s64) = COPY %d1
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; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
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%2(s1) = G_FCMP floatpred(ole), %0(s64), %1
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; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
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; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
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; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
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; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
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%3(s32) = G_ZEXT %2(s1)
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; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
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%r0 = COPY %3(s32)
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; CHECK: %r0 = COPY [[RET]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_fcmp_ord_s64
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# CHECK-LABEL: name: test_fcmp_ord_s64
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: fprb }
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- { id: 1, class: fprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: %d0, %d1
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%0(s64) = COPY %d0
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; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
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%1(s64) = COPY %d1
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; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
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%2(s1) = G_FCMP floatpred(ord), %0(s64), %1
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; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
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; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
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; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
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; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 7, %cpsr
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%3(s32) = G_ZEXT %2(s1)
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; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
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%r0 = COPY %3(s32)
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; CHECK: %r0 = COPY [[RET]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_fcmp_ugt_s64
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# CHECK-LABEL: name: test_fcmp_ugt_s64
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: fprb }
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- { id: 1, class: fprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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body: |
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bb.0:
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liveins: %d0, %d1
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|
||||
%0(s64) = COPY %d0
|
||||
; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
|
||||
|
||||
%1(s64) = COPY %d1
|
||||
; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
|
||||
|
||||
%2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
|
||||
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
|
||||
; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
|
||||
; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
|
||||
|
||||
%3(s32) = G_ZEXT %2(s1)
|
||||
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
|
||||
|
||||
%r0 = COPY %3(s32)
|
||||
; CHECK: %r0 = COPY [[RET]]
|
||||
|
||||
BX_RET 14, _, implicit %r0
|
||||
; CHECK: BX_RET 14, _, implicit %r0
|
||||
...
|
||||
---
|
||||
name: test_fcmp_uge_s64
|
||||
# CHECK-LABEL: name: test_fcmp_uge_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK: selected: true
|
||||
registers:
|
||||
- { id: 0, class: fprb }
|
||||
- { id: 1, class: fprb }
|
||||
- { id: 2, class: gprb }
|
||||
- { id: 3, class: gprb }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0, %d1
|
||||
|
||||
%0(s64) = COPY %d0
|
||||
; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
|
||||
|
||||
%1(s64) = COPY %d1
|
||||
; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
|
||||
|
||||
%2(s1) = G_FCMP floatpred(uge), %0(s64), %1
|
||||
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
|
||||
; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
|
||||
; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 5, %cpsr
|
||||
|
||||
%3(s32) = G_ZEXT %2(s1)
|
||||
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
|
||||
|
||||
%r0 = COPY %3(s32)
|
||||
; CHECK: %r0 = COPY [[RET]]
|
||||
|
||||
BX_RET 14, _, implicit %r0
|
||||
; CHECK: BX_RET 14, _, implicit %r0
|
||||
...
|
||||
---
|
||||
name: test_fcmp_ult_s64
|
||||
# CHECK-LABEL: name: test_fcmp_ult_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK: selected: true
|
||||
registers:
|
||||
- { id: 0, class: fprb }
|
||||
- { id: 1, class: fprb }
|
||||
- { id: 2, class: gprb }
|
||||
- { id: 3, class: gprb }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0, %d1
|
||||
|
||||
%0(s64) = COPY %d0
|
||||
; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
|
||||
|
||||
%1(s64) = COPY %d1
|
||||
; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
|
||||
|
||||
%2(s1) = G_FCMP floatpred(ult), %0(s64), %1
|
||||
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
|
||||
; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
|
||||
; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr
|
||||
|
||||
%3(s32) = G_ZEXT %2(s1)
|
||||
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
|
||||
|
||||
%r0 = COPY %3(s32)
|
||||
; CHECK: %r0 = COPY [[RET]]
|
||||
|
||||
BX_RET 14, _, implicit %r0
|
||||
; CHECK: BX_RET 14, _, implicit %r0
|
||||
...
|
||||
---
|
||||
name: test_fcmp_ule_s64
|
||||
# CHECK-LABEL: name: test_fcmp_ule_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK: selected: true
|
||||
registers:
|
||||
- { id: 0, class: fprb }
|
||||
- { id: 1, class: fprb }
|
||||
- { id: 2, class: gprb }
|
||||
- { id: 3, class: gprb }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0, %d1
|
||||
|
||||
%0(s64) = COPY %d0
|
||||
; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
|
||||
|
||||
%1(s64) = COPY %d1
|
||||
; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
|
||||
|
||||
%2(s1) = G_FCMP floatpred(ule), %0(s64), %1
|
||||
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
|
||||
; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
|
||||
; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr
|
||||
|
||||
%3(s32) = G_ZEXT %2(s1)
|
||||
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
|
||||
|
||||
%r0 = COPY %3(s32)
|
||||
; CHECK: %r0 = COPY [[RET]]
|
||||
|
||||
BX_RET 14, _, implicit %r0
|
||||
; CHECK: BX_RET 14, _, implicit %r0
|
||||
...
|
||||
---
|
||||
name: test_fcmp_une_s64
|
||||
# CHECK-LABEL: name: test_fcmp_une_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK: selected: true
|
||||
registers:
|
||||
- { id: 0, class: fprb }
|
||||
- { id: 1, class: fprb }
|
||||
- { id: 2, class: gprb }
|
||||
- { id: 3, class: gprb }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0, %d1
|
||||
|
||||
%0(s64) = COPY %d0
|
||||
; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
|
||||
|
||||
%1(s64) = COPY %d1
|
||||
; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
|
||||
|
||||
%2(s1) = G_FCMP floatpred(une), %0(s64), %1
|
||||
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
|
||||
; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
|
||||
; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr
|
||||
|
||||
%3(s32) = G_ZEXT %2(s1)
|
||||
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
|
||||
|
||||
%r0 = COPY %3(s32)
|
||||
; CHECK: %r0 = COPY [[RET]]
|
||||
|
||||
BX_RET 14, _, implicit %r0
|
||||
; CHECK: BX_RET 14, _, implicit %r0
|
||||
...
|
||||
---
|
||||
name: test_fcmp_uno_s64
|
||||
# CHECK-LABEL: name: test_fcmp_uno_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK: selected: true
|
||||
registers:
|
||||
- { id: 0, class: fprb }
|
||||
- { id: 1, class: fprb }
|
||||
- { id: 2, class: gprb }
|
||||
- { id: 3, class: gprb }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0, %d1
|
||||
|
||||
%0(s64) = COPY %d0
|
||||
; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
|
||||
|
||||
%1(s64) = COPY %d1
|
||||
; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
|
||||
|
||||
%2(s1) = G_FCMP floatpred(uno), %0(s64), %1
|
||||
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
|
||||
; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
|
||||
; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 6, %cpsr
|
||||
|
||||
%3(s32) = G_ZEXT %2(s1)
|
||||
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
|
||||
|
||||
%r0 = COPY %3(s32)
|
||||
; CHECK: %r0 = COPY [[RET]]
|
||||
|
||||
BX_RET 14, _, implicit %r0
|
||||
; CHECK: BX_RET 14, _, implicit %r0
|
||||
...
|
||||
---
|
||||
name: test_fcmp_one_s64
|
||||
# CHECK-LABEL: name: test_fcmp_one_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK: selected: true
|
||||
registers:
|
||||
- { id: 0, class: fprb }
|
||||
- { id: 1, class: fprb }
|
||||
- { id: 2, class: gprb }
|
||||
- { id: 3, class: gprb }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0, %d1
|
||||
|
||||
%0(s64) = COPY %d0
|
||||
; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
|
||||
|
||||
%1(s64) = COPY %d1
|
||||
; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
|
||||
|
||||
%2(s1) = G_FCMP floatpred(one), %0(s64), %1
|
||||
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
|
||||
; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
|
||||
; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
|
||||
; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
|
||||
; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
|
||||
; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 4, %cpsr
|
||||
|
||||
%3(s32) = G_ZEXT %2(s1)
|
||||
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
|
||||
|
||||
%r0 = COPY %3(s32)
|
||||
; CHECK: %r0 = COPY [[RET]]
|
||||
|
||||
BX_RET 14, _, implicit %r0
|
||||
; CHECK: BX_RET 14, _, implicit %r0
|
||||
...
|
||||
---
|
||||
name: test_fcmp_ueq_s64
|
||||
# CHECK-LABEL: name: test_fcmp_ueq_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK: selected: true
|
||||
registers:
|
||||
- { id: 0, class: fprb }
|
||||
- { id: 1, class: fprb }
|
||||
- { id: 2, class: gprb }
|
||||
- { id: 3, class: gprb }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0, %d1
|
||||
|
||||
%0(s64) = COPY %d0
|
||||
; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
|
||||
|
||||
%1(s64) = COPY %d1
|
||||
; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
|
||||
|
||||
%2(s1) = G_FCMP floatpred(ueq), %0(s64), %1
|
||||
; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
|
||||
; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
|
||||
; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
|
||||
; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
|
||||
; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
|
||||
; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
|
||||
; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 6, %cpsr
|
||||
|
||||
%3(s32) = G_ZEXT %2(s1)
|
||||
; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
|
||||
|
||||
%r0 = COPY %3(s32)
|
||||
; CHECK: %r0 = COPY [[RET]]
|
||||
|
||||
BX_RET 14, _, implicit %r0
|
||||
; CHECK: BX_RET 14, _, implicit %r0
|
||||
...
|
||||
|
||||
Loading…
Reference in New Issue
Block a user