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[AMDGPU] Enable absolute expression initializer for amd_kernel_code_t fields.
Differential Revision: http://reviews.llvm.org/D21380 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273561 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Valery Pykhtin
parent
c1faee3baa
commit
85d254114e
@ -1277,7 +1277,7 @@ bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
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amd_kernel_code_t &Header) {
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SmallString<40> ErrStr;
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raw_svector_ostream Err(ErrStr);
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if (!parseAmdKernelCodeField(ID, getLexer(), Header, Err)) {
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if (!parseAmdKernelCodeField(ID, getParser(), Header, Err)) {
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return TokError(Err.str());
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}
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Lex();
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@ -1291,9 +1291,6 @@ bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
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while (true) {
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if (getLexer().isNot(AsmToken::EndOfStatement))
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return TokError("amd_kernel_code_t values must begin on a new line");
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// Lex EndOfStatement. This is in a while loop, because lexing a comment
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// will set the current token to EndOfStatement.
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while(getLexer().is(AsmToken::EndOfStatement))
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@ -37,15 +37,15 @@
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// have to define these lambdas because of Set/GetMacro
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#define PRINTCOMP(GetMacro, Shift) \
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[](StringRef Name, const amd_kernel_code_t& C, raw_ostream& OS) { \
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[](StringRef Name, const amd_kernel_code_t &C, raw_ostream &OS) { \
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printName(OS, Name) << \
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(int)GetMacro(C.compute_pgm_resource_registers >> Shift); \
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}
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#define PARSECOMP(SetMacro, Shift) \
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[](amd_kernel_code_t& C, MCAsmLexer& Lexer, raw_ostream& Err) { \
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if (!expectEqualInt(Lexer, Err)) \
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[](amd_kernel_code_t &C, MCAsmParser &MCParser, raw_ostream &Err) { \
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int64_t Value = 0; \
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if (!expectAbsExpression(MCParser, Value, Err)) \
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return false; \
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const uint64_t Value = Lexer.getTok().getIntVal(); \
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C.compute_pgm_resource_registers |= SetMacro(Value) << Shift; \
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return true; \
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}
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@ -16,6 +16,7 @@
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#include "AMDKernelCodeTUtils.h"
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#include "SIDefines.h"
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#include <llvm/MC/MCParser/MCAsmLexer.h>
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#include <llvm/MC/MCParser/MCAsmParser.h>
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#include <llvm/Support/raw_ostream.h>
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using namespace llvm;
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@ -101,41 +102,45 @@ void llvm::dumpAmdKernelCode(const amd_kernel_code_t *C,
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// Field parsing
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static bool expectEqualInt(MCAsmLexer &Lexer, raw_ostream &Err) {
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if (Lexer.isNot(AsmToken::Equal)) {
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static bool expectAbsExpression(MCAsmParser &MCParser, int64_t &Value, raw_ostream& Err) {
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if (MCParser.getLexer().isNot(AsmToken::Equal)) {
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Err << "expected '='";
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return false;
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}
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Lexer.Lex();
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if (Lexer.isNot(AsmToken::Integer)) {
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Err << "integer literal expected";
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MCParser.getLexer().Lex();
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if (MCParser.parseAbsoluteExpression(Value)) {
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Err << "integer absolute expression expected";
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return false;
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}
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return true;
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}
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template <typename T, T amd_kernel_code_t::*ptr>
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static bool parseField(amd_kernel_code_t &C, MCAsmLexer &Lexer,
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static bool parseField(amd_kernel_code_t &C, MCAsmParser &MCParser,
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raw_ostream &Err) {
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if (!expectEqualInt(Lexer, Err))
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int64_t Value = 0;
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if (!expectAbsExpression(MCParser, Value, Err))
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return false;
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C.*ptr = (T)Lexer.getTok().getIntVal();
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C.*ptr = (T)Value;
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return true;
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}
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template <typename T, T amd_kernel_code_t::*ptr, int shift, int width = 1>
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static bool parseBitField(amd_kernel_code_t &C, MCAsmLexer &Lexer,
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static bool parseBitField(amd_kernel_code_t &C, MCAsmParser &MCParser,
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raw_ostream &Err) {
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if (!expectEqualInt(Lexer, Err))
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int64_t Value = 0;
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if (!expectAbsExpression(MCParser, Value, Err))
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return false;
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const uint64_t Mask = ((UINT64_C(1) << width) - 1) << shift;
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C.*ptr &= (T)~Mask;
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C.*ptr |= (T)((Lexer.getTok().getIntVal() << shift) & Mask);
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C.*ptr |= (T)((Value << shift) & Mask);
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return true;
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}
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typedef bool(*ParseFx)(amd_kernel_code_t &,
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MCAsmLexer &Lexer,
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MCAsmParser &MCParser,
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raw_ostream &Err);
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static ArrayRef<ParseFx> getParserTable() {
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@ -148,7 +153,7 @@ static ArrayRef<ParseFx> getParserTable() {
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}
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bool llvm::parseAmdKernelCodeField(StringRef ID,
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MCAsmLexer &Lexer,
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MCAsmParser &MCParser,
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amd_kernel_code_t &C,
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raw_ostream &Err) {
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const int Idx = get_amd_kernel_code_t_FieldIndex(ID);
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@ -157,5 +162,5 @@ bool llvm::parseAmdKernelCodeField(StringRef ID,
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return false;
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}
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auto Parser = getParserTable()[Idx];
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return Parser ? Parser(C, Lexer, Err) : false;
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return Parser ? Parser(C, MCParser, Err) : false;
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}
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@ -17,6 +17,7 @@
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namespace llvm {
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class MCAsmLexer;
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class MCAsmParser;
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class raw_ostream;
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class StringRef;
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@ -29,7 +30,7 @@ void dumpAmdKernelCode(const amd_kernel_code_t *C,
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const char *tab);
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bool parseAmdKernelCodeField(StringRef ID,
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MCAsmLexer &Lexer,
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MCAsmParser &Parser,
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amd_kernel_code_t &C,
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raw_ostream &Err);
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129
test/MC/AMDGPU/hsa-exp.s
Normal file
129
test/MC/AMDGPU/hsa-exp.s
Normal file
@ -0,0 +1,129 @@
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// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM
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// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF
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// ELF: Section {
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// ELF: Name: .text
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// ELF: Type: SHT_PROGBITS (0x1)
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// ELF: Flags [ (0x6)
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// ELF: SHF_ALLOC (0x2)
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// ELF: SHF_EXECINSTR (0x4)
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// ELF: SHT_NOTE
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// ELF: 0000: 04000000 08000000 01000000 414D4400
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// ELF: 0010: 02000000 00000000 04000000 1B000000
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// ELF: 0020: 03000000 414D4400 04000700 07000000
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// ELF: 0030: 00000000 00000000 414D4400 414D4447
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// ELF: 0040: 50550000
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// ELF: Symbol {
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// ELF: Name: amd_kernel_code_t_minimal
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// ELF: Type: AMDGPU_HSA_KERNEL (0xA)
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// ELF: Section: .text
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// ELF: }
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.text
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// ASM: .text
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.hsa_code_object_version 2,0
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// ASM: .hsa_code_object_version 2,0
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.hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
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// ASM: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
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.amdgpu_hsa_kernel amd_kernel_code_t_minimal
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.set my_is_ptr64, 1
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.if my_is_ptr64 == 0
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.set my_kernarg_segment_byte_size, 32
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.else
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.set my_kernarg_segment_byte_size, 16
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.endif
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.set my_sgpr, 8
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amd_kernel_code_t_minimal:
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.amd_kernel_code_t
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kernel_code_version_major = .option.machine_version_major
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enable_sgpr_kernarg_segment_ptr = 1
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is_ptr64 = my_is_ptr64
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compute_pgm_rsrc1_vgprs = 1
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compute_pgm_rsrc1_sgprs = 1+(my_sgpr-1)/8
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compute_pgm_rsrc2_user_sgpr = 2
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kernarg_segment_byte_size = my_kernarg_segment_byte_size
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wavefront_sgpr_count = my_sgpr
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// wavefront_sgpr_count = 7
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; wavefront_sgpr_count = 7
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// Make sure a blank line won't break anything:
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// Make sure a line with whitespace won't break anything:
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workitem_vgpr_count = 16
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.end_amd_kernel_code_t
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// ASM-LABEL: {{^}}amd_kernel_code_t_minimal:
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// ASM: .amd_kernel_code_t
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// ASM: kernel_code_version_major = 7
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// ASM: kernel_code_version_minor = 0
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// ASM: machine_kind = 1
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// ASM: machine_version_major = 7
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// ASM: machine_version_minor = 0
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// ASM: machine_version_stepping = 0
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// ASM: kernel_code_entry_byte_offset = 256
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// ASM: kernel_code_prefetch_byte_size = 0
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// ASM: max_scratch_backing_memory_byte_size = 0
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// ASM: compute_pgm_rsrc1_vgprs = 1
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// ASM: compute_pgm_rsrc1_sgprs = 1
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// ASM: compute_pgm_rsrc1_priority = 0
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// ASM: compute_pgm_rsrc1_float_mode = 0
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// ASM: compute_pgm_rsrc1_priv = 0
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// ASM: compute_pgm_rsrc1_dx10_clamp = 0
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// ASM: compute_pgm_rsrc1_debug_mode = 0
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// ASM: compute_pgm_rsrc1_ieee_mode = 0
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// ASM: compute_pgm_rsrc2_scratch_en = 0
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// ASM: compute_pgm_rsrc2_user_sgpr = 2
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// ASM: compute_pgm_rsrc2_tgid_x_en = 0
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// ASM: compute_pgm_rsrc2_tgid_y_en = 0
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// ASM: compute_pgm_rsrc2_tgid_z_en = 0
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// ASM: compute_pgm_rsrc2_tg_size_en = 0
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// ASM: compute_pgm_rsrc2_tidig_comp_cnt = 0
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// ASM: compute_pgm_rsrc2_excp_en_msb = 0
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// ASM: compute_pgm_rsrc2_lds_size = 0
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// ASM: compute_pgm_rsrc2_excp_en = 0
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// ASM: enable_sgpr_private_segment_buffer = 0
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// ASM: enable_sgpr_dispatch_ptr = 0
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// ASM: enable_sgpr_queue_ptr = 0
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// ASM: enable_sgpr_kernarg_segment_ptr = 1
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// ASM: enable_sgpr_dispatch_id = 0
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// ASM: enable_sgpr_flat_scratch_init = 0
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// ASM: enable_sgpr_private_segment_size = 0
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// ASM: enable_sgpr_grid_workgroup_count_x = 0
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// ASM: enable_sgpr_grid_workgroup_count_y = 0
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// ASM: enable_sgpr_grid_workgroup_count_z = 0
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// ASM: enable_ordered_append_gds = 0
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// ASM: private_element_size = 0
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// ASM: is_ptr64 = 1
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// ASM: is_dynamic_callstack = 0
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// ASM: is_debug_enabled = 0
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// ASM: is_xnack_enabled = 0
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// ASM: workitem_private_segment_byte_size = 0
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// ASM: workgroup_group_segment_byte_size = 0
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// ASM: gds_segment_byte_size = 0
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// ASM: kernarg_segment_byte_size = 16
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// ASM: workgroup_fbarrier_count = 0
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// ASM: wavefront_sgpr_count = 8
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// ASM: workitem_vgpr_count = 16
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// ASM: reserved_vgpr_first = 0
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// ASM: reserved_vgpr_count = 0
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// ASM: reserved_sgpr_first = 0
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// ASM: reserved_sgpr_count = 0
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// ASM: debug_wavefront_private_segment_offset_sgpr = 0
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// ASM: debug_private_segment_buffer_sgpr = 0
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// ASM: kernarg_segment_alignment = 4
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// ASM: group_segment_alignment = 4
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// ASM: private_segment_alignment = 4
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// ASM: wavefront_size = 6
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// ASM: call_convention = 0
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// ASM: runtime_loader_kernel_symbol = 0
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// ASM: .end_amd_kernel_code_t
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