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Added NOP, DBG, SVC to the instruction table for disassembly purpose.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95784 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-02-10 18:02:25 +00:00
parent f451cb870e
commit 85d5a89f8d
1 changed files with 20 additions and 0 deletions
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20
lib/Target/ARM/ARMInstrInfo.td
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@ -605,6 +605,20 @@ PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
[(ARMcallseq_start timm:$amt)]>; [(ARMcallseq_start timm:$amt)]>;
} }
def NOP : AI<(outs), (ins), Pseudo, NoItinerary, "nop", "",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6T2]> {
let Inst{27-16} = 0b001100100000;
let Inst{7-0} = 0b00000000;
}
def DBG : AI<(outs), (ins i32imm:$opt), Pseudo, NoItinerary, "dbg", "\t$opt",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV7]> {
let Inst{27-16} = 0b001100100000;
let Inst{7-4} = 0b1111;
}
// Address computation and loads and stores in PIC mode. // Address computation and loads and stores in PIC mode.
let isNotDuplicable = 1 in { let isNotDuplicable = 1 in {
def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
@ -827,6 +841,12 @@ let isBranch = 1, isTerminator = 1 in {
[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
} }
// Supervisor call (software interrupt) -- for disassembly only
let isCall = 1 in {
def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
[/* For disassembly only; pattern left blank */]>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Load / store Instructions. // Load / store Instructions.
// //