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Expand ret into "CopyToReg;BRIND"

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28559 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-05-30 17:33:19 +00:00
parent 73faa39d29
commit 85ede37ca9
2 changed files with 4 additions and 18 deletions
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12
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -28,13 +28,6 @@
#include <set>
using namespace llvm;
namespace ARMISD {
enum {
FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
RET_FLAG
};
}
namespace {
class ARMTargetLowering : public TargetLowering {
public:
@ -63,11 +56,12 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
case 1:
return SDOperand(); // ret void is legal
case 3:
Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(2), SDOperand());
Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
break;
}
SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR);
}
static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {

10
lib/Target/ARM/ARMInstrInfo.td
View File

@ -30,10 +30,6 @@ def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]>;
def SDT_ARMRetFlag : SDTypeProfile<0, 0, []>;
def retflag : SDNode<"ARMISD::RET_FLAG", SDT_ARMRetFlag,
[SDNPHasChain, SDNPOptInFlag]>;
def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKUP $amt",
[(callseq_end imm:$amt)]>;
@ -42,11 +38,7 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
[(callseq_start imm:$amt)]>;
//bx supports other registers as operands. So this looks like a
//hack. Maybe a ret should be expanded to a "branch lr" and bx
//declared as a regular instruction
def BX: InstARM<(ops), "bx lr", [(retflag)]>;
def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
"ldr $dst, [$addr]",