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'svn add' the test cases.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190929 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joey Gouly 2013-09-18 09:46:49 +00:00
parent a4d46d7fc6
commit 8634b0ee47
5 changed files with 92 additions and 0 deletions
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23
test/MC/ARM/crc32-thumb.s Normal file
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@ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s
@ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
crc32b r0, r1, r2
crc32h r0, r1, r2
crc32w r0, r1, r2
@ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0]
@ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0]
@ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0]
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
crc32cb r0, r1, r2
crc32ch r0, r1, r2
crc32cw r0, r1, r2
@ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0]
@ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0]
@ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0]
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8

23
test/MC/ARM/crc32.s Normal file
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@ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s
@ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
crc32b r0, r1, r2
crc32h r0, r1, r2
crc32w r0, r1, r2
@ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1]
@ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1]
@ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1]
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
crc32cb r0, r1, r2
crc32ch r0, r1, r2
crc32cw r0, r1, r2
@ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1]
@ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1]
@ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1]
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8
@ CHECK-V7: error: instruction requires: armv8

16
test/MC/ARM/invalid-crc32.s Normal file
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@ RUN: not llvm-mc -triple=armv8 -show-encoding < %s 2>&1 | FileCheck %s
@ RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck %s
crc32cbeq r0, r1, r2
crc32bne r0, r1, r2
crc32chcc r0, r1, r2
crc32hpl r0, r1, r2
crc32cwgt r0, r1, r2
crc32wle r0, r1, r2
@ CHECK: error: instruction 'crc32cb' is not predicable, but condition code specified
@ CHECK: error: instruction 'crc32b' is not predicable, but condition code specified
@ CHECK: error: instruction 'crc32ch' is not predicable, but condition code specified
@ CHECK: error: instruction 'crc32h' is not predicable, but condition code specified
@ CHECK: error: instruction 'crc32cw' is not predicable, but condition code specified
@ CHECK: error: instruction 'crc32w' is not predicable, but condition code specified

15
test/MC/Disassembler/ARM/crc32-thumb.txt Normal file
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# RUN: llvm-mc --disassemble %s -triple=thumbv8 2>&1 | FileCheck %s
# CHECK: crc32b r0, r1, r2
# CHECK: crc32h r0, r1, r2
# CHECK: crc32w r0, r1, r2
# CHECK: crc32cb r0, r1, r2
# CHECK: crc32ch r0, r1, r2
# CHECK: crc32cw r0, r1, r2
0xc1 0xfa 0x82 0xf0
0xc1 0xfa 0x92 0xf0
0xc1 0xfa 0xa2 0xf0
0xd1 0xfa 0x82 0xf0
0xd1 0xfa 0x92 0xf0
0xd1 0xfa 0xa2 0xf0

15
test/MC/Disassembler/ARM/crc32.txt Normal file
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# RUN: llvm-mc --disassemble %s -triple=armv8 2>&1 | FileCheck %s
# CHECK: crc32b r0, r1, r2
# CHECK: crc32h r0, r1, r2
# CHECK: crc32w r0, r1, r2
# CHECK: crc32cb r0, r1, r2
# CHECK: crc32ch r0, r1, r2
# CHECK: crc32cw r0, r1, r2
0x42 0x00 0x01 0xe1
0x42 0x00 0x21 0xe1
0x42 0x00 0x41 0xe1
0x42 0x02 0x01 0xe1
0x42 0x02 0x21 0xe1
0x42 0x02 0x41 0xe1