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R600/SI: Use unordered not equal instructions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224065 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-12-11 22:15:35 +00:00
parent 05e5839d4f
commit 8651adfe4f
8 changed files with 25 additions and 26 deletions
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18
lib/Target/R600/AMDGPUInstructions.td
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@ -73,6 +73,11 @@ def COND_OEQ : PatLeaf <
[{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
>;
def COND_ONE : PatLeaf <
(cond),
[{return N->get() == ISD::SETONE || N->get() == ISD::SETNE;}]
>;
def COND_OGT : PatLeaf <
(cond),
[{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
@ -93,10 +98,6 @@ def COND_OLE : PatLeaf <
[{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
>;
def COND_UNE : PatLeaf <
(cond),
[{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
>;
def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
@ -105,11 +106,20 @@ def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
// PatLeafs for unsigned comparisons
//===----------------------------------------------------------------------===//
def COND_UEQ : PatLeaf <(cond), [{return N->get() == ISD::SETUEQ;}]>;
def COND_UNE : PatLeaf <(cond), [{return N->get() == ISD::SETUNE;}]>;
def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
// XXX - For some reason R600 version is preferring to use unordered
// for setne?
def COND_UNE_NE : PatLeaf <
(cond),
[{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
>;
//===----------------------------------------------------------------------===//
// PatLeafs for signed comparisons
//===----------------------------------------------------------------------===//

5
lib/Target/R600/R600Instructions.td
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@ -698,7 +698,7 @@ def SGE : R600_2OP <
def SNE : R600_2OP <
0xB, "SETNE",
[(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE))]
[(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE_NE))]
>;
def SETE_DX10 : R600_2OP <
@ -716,9 +716,10 @@ def SETGE_DX10 : R600_2OP <
[(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))]
>;
// FIXME: This should probably be COND_ONE
def SETNE_DX10 : R600_2OP <
0xF, "SETNE_DX10",
[(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE))]
[(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE_NE))]
>;
def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;

2
lib/Target/R600/SIISelLowering.cpp
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@ -62,14 +62,12 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
computeRegisterProperties();
// Condition Codes
setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);

4
lib/Target/R600/SIInstructions.td
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@ -506,7 +506,7 @@ defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT>;
defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>;
defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE>;
defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>;
defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32">;
defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>;
defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>;
defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>;
defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>;
@ -544,7 +544,7 @@ defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT>;
defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>;
defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE>;
defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>;
defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64">;
defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>;
defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>;
defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>;
defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>;

4
test/CodeGen/R600/fceil64.ll
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@ -22,9 +22,7 @@ declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone
; SI: cmp_gt_i32
; SI: cndmask_b32
; SI: cndmask_b32
; SI: v_cmp_o_f64
; SI: v_cmp_neq_f64
; SI: s_and_b64
; SI: v_cmp_lg_f64
; SI: v_cmp_gt_f64
; SI: s_and_b64
; SI: v_cndmask_b32

4
test/CodeGen/R600/ffloor.ll
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@ -23,9 +23,7 @@ declare <16 x double> @llvm.floor.v16f64(<16 x double>) nounwind readnone
; SI: cmp_gt_i32
; SI: cndmask_b32
; SI: cndmask_b32
; SI: v_cmp_o_f64
; SI: v_cmp_neq_f64
; SI: s_and_b64
; SI: v_cmp_lg_f64
; SI: v_cmp_lt_f64
; SI: s_and_b64
; SI: v_cndmask_b32

7
test/CodeGen/R600/setcc.ll
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@ -97,11 +97,8 @@ entry:
; R600-DAG: AND_INT
; R600-DAG: SETNE_INT
; SI-DAG: v_cmp_o_f32_e32 vcc
; SI-DAG: v_cmp_neq_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
; SI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP1]], vcc
; SI: v_cndmask_b32_e64 [[VRESULT:v[0-9]+]], 0, -1, [[AND]]
; SI: buffer_store_dword [[VRESULT]]
; SI: v_cmp_lg_f32_e32 vcc
; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
define void @f32_one(i32 addrspace(1)* %out, float %a, float %b) {
entry:
%0 = fcmp one float %a, %b

7
test/CodeGen/R600/setcc64.ll
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@ -57,11 +57,8 @@ entry:
}
; FUNC-LABEL: {{^}}f64_one:
; SI-DAG: v_cmp_o_f64_e32 vcc
; SI-DAG: v_cmp_neq_f64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
; SI: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP1]], vcc
; SI: v_cndmask_b32_e64 [[VRESULT:v[0-9]+]], 0, -1, [[AND]]
; SI: buffer_store_dword [[VRESULT]]
; SI: v_cmp_lg_f64_e32 vcc
; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
define void @f64_one(i32 addrspace(1)* %out, double %a, double %b) {
entry:
%0 = fcmp one double %a, %b