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1. Support ELF pcrel relocations for movw/movt:
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC. 2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum. 3. Add support for 3 new elf section types (no-ops) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123294 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jason W Kim
parent
9081b4b4cf
commit
86a97f2e4d
@ -1268,6 +1268,9 @@ void ELFObjectWriter::WriteSection(MCAssembler &Asm,
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case ELF::SHT_NOTE:
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case ELF::SHT_NULL:
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case ELF::SHT_ARM_ATTRIBUTES:
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case ELF::SHT_INIT_ARRAY:
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case ELF::SHT_FINI_ARRAY:
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case ELF::SHT_PREINIT_ARRAY:
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// Nothing to do.
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break;
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@ -1490,6 +1493,13 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
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default:
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Type = ELF::R_ARM_CALL; break;
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} break;
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case ARM::fixup_arm_movt_hi16:
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case ARM::fixup_arm_movt_hi16_pcrel:
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Type = ELF::R_ARM_MOVT_PREL; break;
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case ARM::fixup_arm_movw_lo16:
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case ARM::fixup_arm_movw_lo16_pcrel:
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Type = ELF::R_ARM_MOVW_PREL_NC; break;
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}
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} else {
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switch ((unsigned)Fixup.getKind()) {
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@ -78,6 +78,8 @@ public:
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{ "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_movt_hi16", 0, 16, 0 },
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{ "fixup_arm_movw_lo16", 0, 16, 0 },
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{ "fixup_arm_movt_hi16_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_movw_lo16_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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};
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if (Kind < FirstTargetFixupKind)
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@ -156,7 +158,9 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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case FK_Data_4:
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return Value;
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case ARM::fixup_arm_movt_hi16:
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case ARM::fixup_arm_movw_lo16: {
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case ARM::fixup_arm_movw_lo16:
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case ARM::fixup_arm_movt_hi16_pcrel:
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case ARM::fixup_arm_movw_lo16_pcrel: {
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unsigned Hi4 = (Value & 0xF000) >> 12;
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unsigned Lo12 = Value & 0x0FFF;
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// inst{19-16} = Hi4;
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@ -189,10 +189,10 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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int64_t Imm = MO.getImm();
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O << '#';
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if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
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(TF == ARMII::MO_LO16))
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(TF & ARMII::MO_LO16))
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O << ":lower16:";
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else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
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(TF == ARMII::MO_HI16))
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(TF & ARMII::MO_HI16))
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O << ":upper16:";
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O << Imm;
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break;
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@ -74,6 +74,11 @@ enum Fixups {
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fixup_arm_movt_hi16, // :upper16:
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fixup_arm_movw_lo16, // :lower16:
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// It is possible to create an "immediate" that happens to be pcrel.
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// Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC
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fixup_arm_movt_hi16_pcrel, // :upper16:
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fixup_arm_movw_lo16_pcrel, // :lower16:
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// Marker
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LastTargetFixupKind,
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NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
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@ -626,6 +626,32 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
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return Binary;
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}
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// FIXME: This routine needs to handle more MCExpr types
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static const MCSymbolRefExpr *FindLHSymExpr(const MCExpr *E) {
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// recurse left child until finding a MCSymbolRefExpr
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switch (E->getKind()) {
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case MCExpr::SymbolRef:
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return cast<MCSymbolRefExpr>(E);
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case MCExpr::Binary:
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return FindLHSymExpr(cast<MCBinaryExpr>(E)->getLHS());
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default:
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return NULL;
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}
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}
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// FIXME: This routine assumes that a binary
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// expression will always result in a PCRel expression
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// In reality, its only true if one or more subexpressions
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// is itself a PCRel (i.e. "." in asm or some other pcrel construct)
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// but this is good enough for now.
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static bool EvaluateAsPCRel(const MCExpr *Expr) {
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switch (Expr->getKind()) {
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case MCExpr::SymbolRef: return false;
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case MCExpr::Binary: return true;
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default: assert(0 && "Unexpected expression type");
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}
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}
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uint32_t ARMMCCodeEmitter::
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getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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@ -635,18 +661,27 @@ getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
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if (MO.isImm()) {
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return static_cast<unsigned>(MO.getImm());
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} else if (const MCSymbolRefExpr *Expr =
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dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
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FindLHSymExpr(MO.getExpr())) {
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// FIXME: :lower16: and :upper16: should be applicable to
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// to whole expression, not just symbolrefs
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// Until that change takes place, this hack is required to
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// generate working code.
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const MCExpr *OrigExpr = MO.getExpr();
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MCFixupKind Kind;
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switch (Expr->getKind()) {
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default: assert(0 && "Unsupported ARMFixup");
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case MCSymbolRefExpr::VK_ARM_HI16:
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Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
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if (EvaluateAsPCRel(OrigExpr))
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Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel);
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break;
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case MCSymbolRefExpr::VK_ARM_LO16:
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Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
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if (EvaluateAsPCRel(OrigExpr))
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Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel);
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break;
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}
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Fixups.push_back(MCFixup::Create(0, Expr, Kind));
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Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind));
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return 0;
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};
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llvm_unreachable("Unsupported MCExpr type in MCOperand!");
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@ -1,4 +1,6 @@
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@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s
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@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \
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@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s
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.syntax unified
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.text
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.globl barf
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@ -12,3 +14,26 @@ barf: @ @barf
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@ ASM: movw r0, :lower16:GOT-(.LPC0_2+8)
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@ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16)
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@@ make sure that the text section fixups are sane too
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@ OBJ: '.text'
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@ OBJ-NEXT: 'sh_type', 0x00000001
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@ OBJ-NEXT: 'sh_flags', 0x00000006
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@ OBJ-NEXT: 'sh_addr', 0x00000000
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@ OBJ-NEXT: 'sh_offset', 0x00000034
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@ OBJ-NEXT: 'sh_size', 0x00000008
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@ OBJ-NEXT: 'sh_link', 0x00000000
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@ OBJ-NEXT: 'sh_info', 0x00000000
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@ OBJ-NEXT: 'sh_addralign', 0x00000004
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@ OBJ-NEXT: 'sh_entsize', 0x00000000
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@ OBJ-NEXT: '_section_data', 'f00f0fe3 ec0f4fe3'
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@ OBJ: Relocation 0x00000000
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@ OBJ-NEXT: 'r_offset', 0x00000000
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@ OBJ-NEXT: 'r_sym'
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@ OBJ-NEXT: 'r_type', 0x0000002d
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@ OBJ: Relocation 0x00000001
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@ OBJ-NEXT: 'r_offset', 0x00000004
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@ OBJ-NEXT: 'r_sym'
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@ OBJ-NEXT: 'r_type', 0x0000002e
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