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[X86][SSE] Improve support for 128-bit vector sign extension
This patch improves support for sign extension of the lower lanes of vectors of integers by making use of the SSE41 pmovsx* sign extension instructions where possible, and optimizing the sign extension by shifts on pre-SSE41 targets (avoiding the use of i64 arithmetic shifts which require scalarization). It converts SIGN_EXTEND nodes to SIGN_EXTEND_VECTOR_INREG where necessary, that more closely matches the pmovsx* instruction than the default approach of using SIGN_EXTEND_INREG which splits the operation (into an ANY_EXTEND lowered to a shuffle followed by shifts) making instruction matching difficult during lowering. Necessary support for SIGN_EXTEND_VECTOR_INREG has been added to the DAGCombiner. Differential Revision: http://reviews.llvm.org/D9848 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237885 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
cebe8f8b05
commit
87d1836793
@ -268,6 +268,7 @@ namespace {
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SDValue visitZERO_EXTEND(SDNode *N);
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SDValue visitANY_EXTEND(SDNode *N);
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SDValue visitSIGN_EXTEND_INREG(SDNode *N);
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SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
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SDValue visitTRUNCATE(SDNode *N);
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SDValue visitBITCAST(SDNode *N);
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SDValue visitBUILD_PAIR(SDNode *N);
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@ -1347,6 +1348,7 @@ SDValue DAGCombiner::visit(SDNode *N) {
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case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
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case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
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case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
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case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
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case ISD::TRUNCATE: return visitTRUNCATE(N);
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case ISD::BITCAST: return visitBITCAST(N);
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case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
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@ -5541,7 +5543,8 @@ static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
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EVT VT = N->getValueType(0);
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assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
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Opcode == ISD::ANY_EXTEND) && "Expected EXTEND dag node in input!");
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Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
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&& "Expected EXTEND dag node in input!");
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// fold (sext c1) -> c1
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// fold (zext c1) -> c1
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@ -5563,7 +5566,7 @@ static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
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unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
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unsigned ShAmt = VTBits - EVTBits;
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SmallVector<SDValue, 8> Elts;
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unsigned NumElts = N0->getNumOperands();
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unsigned NumElts = VT.getVectorNumElements();
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SDLoc DL(N);
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for (unsigned i=0; i != NumElts; ++i) {
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@ -5576,7 +5579,7 @@ static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
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SDLoc DL(Op);
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ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
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const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
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if (Opcode == ISD::SIGN_EXTEND)
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if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
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Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
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DL, SVT));
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else
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@ -6805,6 +6808,20 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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return SDValue();
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}
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SDValue DAGCombiner::visitSIGN_EXTEND_VECTOR_INREG(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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if (N0.getOpcode() == ISD::UNDEF)
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return DAG.getUNDEF(VT);
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if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
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LegalOperations))
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return SDValue(Res, 0);
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return SDValue();
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}
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SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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@ -3429,12 +3429,35 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
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assert(EVT.bitsLE(VT) && "Not extending!");
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if (EVT == VT) return N1; // Not actually extending
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auto SignExtendInReg = [&](APInt Val) {
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unsigned FromBits = EVT.getScalarType().getSizeInBits();
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Val <<= Val.getBitWidth() - FromBits;
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Val = Val.ashr(Val.getBitWidth() - FromBits);
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return getConstant(Val, DL, VT.getScalarType());
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};
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if (N1C) {
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APInt Val = N1C->getAPIntValue();
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unsigned FromBits = EVT.getScalarType().getSizeInBits();
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Val <<= Val.getBitWidth()-FromBits;
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Val = Val.ashr(Val.getBitWidth()-FromBits);
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return getConstant(Val, DL, VT);
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return SignExtendInReg(Val);
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}
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if (ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
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SmallVector<SDValue, 8> Ops;
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for (int i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
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SDValue Op = N1.getOperand(i);
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if (Op.getValueType() != VT.getScalarType()) break;
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if (Op.getOpcode() == ISD::UNDEF) {
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Ops.push_back(Op);
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continue;
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}
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getNode())) {
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APInt Val = C->getAPIntValue();
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Ops.push_back(SignExtendInReg(Val));
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continue;
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}
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break;
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}
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if (Ops.size() == VT.getVectorNumElements())
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return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
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}
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break;
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}
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@ -1004,6 +1004,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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}
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if (Subtarget->hasSSE2()) {
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
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setOperationAction(ISD::SRL, MVT::v8i16, Custom);
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setOperationAction(ISD::SRL, MVT::v16i8, Custom);
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@ -13914,6 +13918,63 @@ static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget
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return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
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}
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static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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SDValue In = Op->getOperand(0);
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MVT VT = Op->getSimpleValueType(0);
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MVT InVT = In.getSimpleValueType();
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assert(VT.getSizeInBits() == InVT.getSizeInBits());
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MVT SVT = VT.getScalarType();
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MVT InSVT = InVT.getScalarType();
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assert(SVT.getScalarSizeInBits() > InSVT.getScalarSizeInBits());
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if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
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return SDValue();
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if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
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return SDValue();
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SDLoc dl(Op);
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// SSE41 targets can use the pmovsx* instructions directly.
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if (Subtarget->hasSSE41())
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return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
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// pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
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SDValue Curr = In;
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MVT CurrVT = InVT;
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// As SRAI is only available on i16/i32 types, we expand only up to i32
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// and handle i64 separately.
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while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
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Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
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MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
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CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
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Curr = DAG.getNode(ISD::BITCAST, dl, CurrVT, Curr);
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}
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SDValue SignExt = Curr;
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if (CurrVT != InVT) {
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unsigned SignExtShift =
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CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
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SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
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DAG.getConstant(SignExtShift, dl, MVT::i8));
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}
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if (CurrVT == VT)
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return SignExt;
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if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
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SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
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DAG.getConstant(31, dl, MVT::i8));
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SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
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return DAG.getNode(ISD::BITCAST, dl, VT, Ext);
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}
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return SDValue();
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}
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static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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MVT VT = Op->getSimpleValueType(0);
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@ -17580,6 +17641,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
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case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
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case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
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case ISD::SIGN_EXTEND_VECTOR_INREG:
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return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
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case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
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case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
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case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
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@ -23683,16 +23746,19 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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SDLoc dl(N);
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EVT SVT = VT.getScalarType();
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EVT InVT = N0->getValueType(0);
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EVT InSVT = InVT.getScalarType();
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SDLoc DL(N);
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// (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
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// (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
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// This exposes the sext to the sdivrem lowering, so that it directly extends
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// from AH (which we otherwise need to do contortions to access).
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if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
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N0.getValueType() == MVT::i8 && VT == MVT::i32) {
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InVT == MVT::i8 && VT == MVT::i32) {
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SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
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SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
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SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
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N0.getOperand(0), N0.getOperand(1));
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DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
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return R.getValue(1);
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@ -23700,14 +23766,57 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
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if (!DCI.isBeforeLegalizeOps()) {
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if (N0.getValueType() == MVT::i1) {
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SDValue Zero = DAG.getConstant(0, dl, VT);
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SDValue Zero = DAG.getConstant(0, DL, VT);
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SDValue AllOnes =
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DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, VT);
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return DAG.getNode(ISD::SELECT, dl, VT, N0, AllOnes, Zero);
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DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
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return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
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}
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return SDValue();
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}
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if (VT.isVector()) {
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auto ExtendToVec128 = [&DAG](SDLoc DL, SDValue N) {
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EVT InVT = N->getValueType(0);
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EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
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128 / InVT.getScalarSizeInBits());
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SmallVector<SDValue, 8> Opnds(128 / InVT.getSizeInBits(),
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DAG.getUNDEF(InVT));
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Opnds[0] = N;
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return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
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};
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// If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
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// which ensures lowering to X86ISD::VSEXT (pmovsx*).
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if (VT.getSizeInBits() == 128 &&
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(SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
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(InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
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SDValue ExOp = ExtendToVec128(DL, N0);
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return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
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}
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// On pre-AVX2 targets, split into 128-bit nodes of
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// ISD::SIGN_EXTEND_VECTOR_INREG.
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if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
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(SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
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(InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
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unsigned NumVecs = VT.getSizeInBits() / 128;
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unsigned NumSubElts = 128 / SVT.getSizeInBits();
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EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
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EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
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SmallVector<SDValue, 8> Opnds;
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for (unsigned i = 0, Offset = 0; i != NumVecs;
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++i, Offset += NumSubElts) {
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SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
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DAG.getIntPtrConstant(Offset, DL));
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SrcVec = ExtendToVec128(DL, SrcVec);
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SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
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Opnds.push_back(SrcVec);
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}
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return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
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}
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}
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if (!Subtarget->hasFp256())
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return SDValue();
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@ -50,20 +50,22 @@ define <4 x i64> @test3(<4 x i1>* %in) nounwind {
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; CHECK: movq
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; CHECK: shlq
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; CHECK: sarq
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; CHECK: vmovq
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; CHECK: movq
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; CHECK: shlq
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; CHECK: sarq
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; CHECK: vmovq
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; CHECK: vpunpcklqdq
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; CHECK: vmovd
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; CHECK: vpinsrd
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; CHECK: movq
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; CHECK: shlq
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; CHECK: sarq
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; CHECK: vmovq
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; CHECK: vpinsrd
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; CHECK: shlq
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; CHECK: sarq
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; CHECK: vmovq
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; CHECK: vpunpcklqdq
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; CHECK: vpinsrd
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; CHECK: vpmovsxdq
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; CHECK: vmovd
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; CHECK: vpinsrd
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; CHECK: vpmovsxdq
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; CHECK: vinsertf128
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; CHECK: ret
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@ -16,13 +16,9 @@ define <8 x float> @foo1_8(<8 x i8> %src) {
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;
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; CHECK-WIDE-LABEL: foo1_8:
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; CHECK-WIDE: ## BB#0:
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; CHECK-WIDE-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; CHECK-WIDE-NEXT: vpslld $24, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: vpsrad $24, %xmm1, %xmm1
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; CHECK-WIDE-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; CHECK-WIDE-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
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; CHECK-WIDE-NEXT: vpslld $24, %xmm0, %xmm0
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; CHECK-WIDE-NEXT: vpsrad $24, %xmm0, %xmm0
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; CHECK-WIDE-NEXT: vpmovsxbd %xmm0, %xmm1
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; CHECK-WIDE-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; CHECK-WIDE-NEXT: vpmovsxbd %xmm0, %xmm0
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; CHECK-WIDE-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; CHECK-WIDE-NEXT: vcvtdq2ps %ymm0, %ymm0
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; CHECK-WIDE-NEXT: retl
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@ -40,9 +36,7 @@ define <4 x float> @foo1_4(<4 x i8> %src) {
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;
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; CHECK-WIDE-LABEL: foo1_4:
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; CHECK-WIDE: ## BB#0:
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; CHECK-WIDE-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; CHECK-WIDE-NEXT: vpslld $24, %xmm0, %xmm0
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; CHECK-WIDE-NEXT: vpsrad $24, %xmm0, %xmm0
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; CHECK-WIDE-NEXT: vpmovsxbd %xmm0, %xmm0
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; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0
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; CHECK-WIDE-NEXT: retl
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%res = sitofp <4 x i8> %src to <4 x float>
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@ -10,37 +10,30 @@
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define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
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; SSE2-LABEL: sext_8i16_to_8i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSE2-NEXT: # kill: XMM0<def> XMM1<kill>
|
||||
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; SSE2-NEXT: pslld $16, %xmm0
|
||||
; SSE2-NEXT: psrad $16, %xmm0
|
||||
; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
|
||||
; SSE2-NEXT: pslld $16, %xmm1
|
||||
; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
|
||||
; SSE2-NEXT: psrad $16, %xmm2
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
|
||||
; SSE2-NEXT: psrad $16, %xmm1
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: sext_8i16_to_8i32:
|
||||
; SSSE3: # BB#0: # %entry
|
||||
; SSSE3-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSSE3-NEXT: # kill: XMM0<def> XMM1<kill>
|
||||
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; SSSE3-NEXT: pslld $16, %xmm0
|
||||
; SSSE3-NEXT: psrad $16, %xmm0
|
||||
; SSSE3-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
|
||||
; SSSE3-NEXT: pslld $16, %xmm1
|
||||
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
|
||||
; SSSE3-NEXT: psrad $16, %xmm2
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
|
||||
; SSSE3-NEXT: psrad $16, %xmm1
|
||||
; SSSE3-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: sext_8i16_to_8i32:
|
||||
; SSE41: # BB#0: # %entry
|
||||
; SSE41-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSE41-NEXT: pmovzxwd %xmm1, %xmm0
|
||||
; SSE41-NEXT: pslld $16, %xmm0
|
||||
; SSE41-NEXT: psrad $16, %xmm0
|
||||
; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
|
||||
; SSE41-NEXT: pslld $16, %xmm1
|
||||
; SSE41-NEXT: psrad $16, %xmm1
|
||||
; SSE41-NEXT: pmovsxwd %xmm0, %xmm2
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSE41-NEXT: pmovsxwd %xmm0, %xmm1
|
||||
; SSE41-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: sext_8i16_to_8i32:
|
||||
@ -58,13 +51,10 @@ define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp
|
||||
;
|
||||
; X32-SSE41-LABEL: sext_8i16_to_8i32:
|
||||
; X32-SSE41: # BB#0: # %entry
|
||||
; X32-SSE41-NEXT: movdqa %xmm0, %xmm1
|
||||
; X32-SSE41-NEXT: pmovzxwd %xmm1, %xmm0
|
||||
; X32-SSE41-NEXT: pslld $16, %xmm0
|
||||
; X32-SSE41-NEXT: psrad $16, %xmm0
|
||||
; X32-SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
|
||||
; X32-SSE41-NEXT: pslld $16, %xmm1
|
||||
; X32-SSE41-NEXT: psrad $16, %xmm1
|
||||
; X32-SSE41-NEXT: pmovsxwd %xmm0, %xmm2
|
||||
; X32-SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; X32-SSE41-NEXT: pmovsxwd %xmm0, %xmm1
|
||||
; X32-SSE41-NEXT: movdqa %xmm2, %xmm0
|
||||
; X32-SSE41-NEXT: retl
|
||||
entry:
|
||||
%B = sext <8 x i16> %A to <8 x i32>
|
||||
@ -74,68 +64,31 @@ entry:
|
||||
define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
|
||||
; SSE2-LABEL: sext_4i32_to_4i64:
|
||||
; SSE2: # BB#0: # %entry
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
|
||||
; SSE2-NEXT: movd %xmm1, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm2
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
||||
; SSE2-NEXT: movd %xmm1, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm1
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; SSE2-NEXT: movd %xmm0, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm1
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSE2-NEXT: movd %xmm0, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm0
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE2-NEXT: movdqa %xmm0, %xmm2
|
||||
; SSE2-NEXT: psrad $31, %xmm2
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
|
||||
; SSE2-NEXT: movdqa %xmm1, %xmm2
|
||||
; SSE2-NEXT: psrad $31, %xmm2
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: sext_4i32_to_4i64:
|
||||
; SSSE3: # BB#0: # %entry
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
|
||||
; SSSE3-NEXT: movd %xmm1, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm2
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
||||
; SSSE3-NEXT: movd %xmm1, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm1
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; SSSE3-NEXT: movd %xmm0, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm1
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSSE3-NEXT: movd %xmm0, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm0
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
||||
; SSSE3-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSSE3-NEXT: movdqa %xmm0, %xmm2
|
||||
; SSSE3-NEXT: psrad $31, %xmm2
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
|
||||
; SSSE3-NEXT: movdqa %xmm1, %xmm2
|
||||
; SSSE3-NEXT: psrad $31, %xmm2
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: sext_4i32_to_4i64:
|
||||
; SSE41: # BB#0: # %entry
|
||||
; SSE41-NEXT: pmovzxdq %xmm0, %xmm1
|
||||
; SSE41-NEXT: pextrq $1, %xmm1, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm3
|
||||
; SSE41-NEXT: movd %xmm1, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm2
|
||||
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; SSE41-NEXT: pextrq $1, %xmm0, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm3
|
||||
; SSE41-NEXT: movd %xmm0, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm1
|
||||
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
|
||||
; SSE41-NEXT: pmovsxdq %xmm0, %xmm2
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSE41-NEXT: pmovsxdq %xmm0, %xmm1
|
||||
; SSE41-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
@ -154,20 +107,9 @@ define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp
|
||||
;
|
||||
; X32-SSE41-LABEL: sext_4i32_to_4i64:
|
||||
; X32-SSE41: # BB#0: # %entry
|
||||
; X32-SSE41-NEXT: pmovzxdq %xmm0, %xmm2
|
||||
; X32-SSE41-NEXT: movd %xmm2, %eax
|
||||
; X32-SSE41-NEXT: sarl $31, %eax
|
||||
; X32-SSE41-NEXT: pextrd $2, %xmm2, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm2
|
||||
; X32-SSE41-NEXT: sarl $31, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm2
|
||||
; X32-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
|
||||
; X32-SSE41-NEXT: movd %xmm1, %eax
|
||||
; X32-SSE41-NEXT: sarl $31, %eax
|
||||
; X32-SSE41-NEXT: pextrd $2, %xmm1, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm1
|
||||
; X32-SSE41-NEXT: sarl $31, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm1
|
||||
; X32-SSE41-NEXT: pmovsxdq %xmm0, %xmm2
|
||||
; X32-SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; X32-SSE41-NEXT: pmovsxdq %xmm0, %xmm1
|
||||
; X32-SSE41-NEXT: movdqa %xmm2, %xmm0
|
||||
; X32-SSE41-NEXT: retl
|
||||
entry:
|
||||
@ -252,20 +194,26 @@ entry:
|
||||
define <2 x i64> @load_sext_test3(<2 x i8> *%ptr) {
|
||||
; SSE2-LABEL: load_sext_test3:
|
||||
; SSE2: # BB#0: # %entry
|
||||
; SSE2-NEXT: movsbq 1(%rdi), %rax
|
||||
; SSE2-NEXT: movd %rax, %xmm1
|
||||
; SSE2-NEXT: movsbq (%rdi), %rax
|
||||
; SSE2-NEXT: movd %rax, %xmm0
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE2-NEXT: movzwl (%rdi), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm0
|
||||
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
||||
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSE2-NEXT: psrad $31, %xmm1
|
||||
; SSE2-NEXT: psrad $24, %xmm0
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: load_sext_test3:
|
||||
; SSSE3: # BB#0: # %entry
|
||||
; SSSE3-NEXT: movsbq 1(%rdi), %rax
|
||||
; SSSE3-NEXT: movd %rax, %xmm1
|
||||
; SSSE3-NEXT: movsbq (%rdi), %rax
|
||||
; SSSE3-NEXT: movd %rax, %xmm0
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSSE3-NEXT: movzwl (%rdi), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm0
|
||||
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
||||
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; SSSE3-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSSE3-NEXT: psrad $31, %xmm1
|
||||
; SSSE3-NEXT: psrad $24, %xmm0
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: load_sext_test3:
|
||||
@ -292,20 +240,22 @@ entry:
|
||||
define <2 x i64> @load_sext_test4(<2 x i16> *%ptr) {
|
||||
; SSE2-LABEL: load_sext_test4:
|
||||
; SSE2: # BB#0: # %entry
|
||||
; SSE2-NEXT: movswq 2(%rdi), %rax
|
||||
; SSE2-NEXT: movd %rax, %xmm1
|
||||
; SSE2-NEXT: movswq (%rdi), %rax
|
||||
; SSE2-NEXT: movd %rax, %xmm0
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE2-NEXT: movd (%rdi), %xmm0
|
||||
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSE2-NEXT: psrad $31, %xmm1
|
||||
; SSE2-NEXT: psrad $16, %xmm0
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: load_sext_test4:
|
||||
; SSSE3: # BB#0: # %entry
|
||||
; SSSE3-NEXT: movswq 2(%rdi), %rax
|
||||
; SSSE3-NEXT: movd %rax, %xmm1
|
||||
; SSSE3-NEXT: movswq (%rdi), %rax
|
||||
; SSSE3-NEXT: movd %rax, %xmm0
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSSE3-NEXT: movd (%rdi), %xmm0
|
||||
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; SSSE3-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSSE3-NEXT: psrad $31, %xmm1
|
||||
; SSSE3-NEXT: psrad $16, %xmm0
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: load_sext_test4:
|
||||
@ -332,20 +282,18 @@ entry:
|
||||
define <2 x i64> @load_sext_test5(<2 x i32> *%ptr) {
|
||||
; SSE2-LABEL: load_sext_test5:
|
||||
; SSE2: # BB#0: # %entry
|
||||
; SSE2-NEXT: movslq 4(%rdi), %rax
|
||||
; SSE2-NEXT: movd %rax, %xmm1
|
||||
; SSE2-NEXT: movslq (%rdi), %rax
|
||||
; SSE2-NEXT: movd %rax, %xmm0
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE2-NEXT: movq (%rdi), %xmm0
|
||||
; SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSE2-NEXT: psrad $31, %xmm1
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: load_sext_test5:
|
||||
; SSSE3: # BB#0: # %entry
|
||||
; SSSE3-NEXT: movslq 4(%rdi), %rax
|
||||
; SSSE3-NEXT: movd %rax, %xmm1
|
||||
; SSSE3-NEXT: movslq (%rdi), %rax
|
||||
; SSSE3-NEXT: movd %rax, %xmm0
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSSE3-NEXT: movq (%rdi), %xmm0
|
||||
; SSSE3-NEXT: movdqa %xmm0, %xmm1
|
||||
; SSSE3-NEXT: psrad $31, %xmm1
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: load_sext_test5:
|
||||
@ -410,72 +358,35 @@ define <4 x i64> @sext_4i1_to_4i64(<4 x i1> %mask) {
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: pslld $31, %xmm0
|
||||
; SSE2-NEXT: psrad $31, %xmm0
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
|
||||
; SSE2-NEXT: movd %xmm1, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm2
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
||||
; SSE2-NEXT: movd %xmm1, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm1
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; SSE2-NEXT: movd %xmm0, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm1
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSE2-NEXT: movd %xmm0, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm0
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE2-NEXT: movdqa %xmm0, %xmm2
|
||||
; SSE2-NEXT: psrad $31, %xmm2
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
|
||||
; SSE2-NEXT: movdqa %xmm1, %xmm2
|
||||
; SSE2-NEXT: psrad $31, %xmm2
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: sext_4i1_to_4i64:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: pslld $31, %xmm0
|
||||
; SSSE3-NEXT: psrad $31, %xmm0
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
|
||||
; SSSE3-NEXT: movd %xmm1, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm2
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
||||
; SSSE3-NEXT: movd %xmm1, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm1
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; SSSE3-NEXT: movd %xmm0, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm1
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSSE3-NEXT: movd %xmm0, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm0
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
||||
; SSSE3-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSSE3-NEXT: movdqa %xmm0, %xmm2
|
||||
; SSSE3-NEXT: psrad $31, %xmm2
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
|
||||
; SSSE3-NEXT: movdqa %xmm1, %xmm2
|
||||
; SSSE3-NEXT: psrad $31, %xmm2
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: sext_4i1_to_4i64:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: pslld $31, %xmm0
|
||||
; SSE41-NEXT: psrad $31, %xmm0
|
||||
; SSE41-NEXT: pmovzxdq %xmm0, %xmm1
|
||||
; SSE41-NEXT: pextrq $1, %xmm1, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm3
|
||||
; SSE41-NEXT: movd %xmm1, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm2
|
||||
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; SSE41-NEXT: pextrq $1, %xmm0, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm3
|
||||
; SSE41-NEXT: movd %xmm0, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm1
|
||||
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
|
||||
; SSE41-NEXT: pmovsxdq %xmm0, %xmm2
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSE41-NEXT: pmovsxdq %xmm0, %xmm1
|
||||
; SSE41-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
@ -500,20 +411,9 @@ define <4 x i64> @sext_4i1_to_4i64(<4 x i1> %mask) {
|
||||
; X32-SSE41: # BB#0:
|
||||
; X32-SSE41-NEXT: pslld $31, %xmm0
|
||||
; X32-SSE41-NEXT: psrad $31, %xmm0
|
||||
; X32-SSE41-NEXT: pmovzxdq %xmm0, %xmm2
|
||||
; X32-SSE41-NEXT: movd %xmm2, %eax
|
||||
; X32-SSE41-NEXT: sarl $31, %eax
|
||||
; X32-SSE41-NEXT: pextrd $2, %xmm2, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm2
|
||||
; X32-SSE41-NEXT: sarl $31, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm2
|
||||
; X32-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
|
||||
; X32-SSE41-NEXT: movd %xmm1, %eax
|
||||
; X32-SSE41-NEXT: sarl $31, %eax
|
||||
; X32-SSE41-NEXT: pextrd $2, %xmm1, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm1
|
||||
; X32-SSE41-NEXT: sarl $31, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm1
|
||||
; X32-SSE41-NEXT: pmovsxdq %xmm0, %xmm2
|
||||
; X32-SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; X32-SSE41-NEXT: pmovsxdq %xmm0, %xmm1
|
||||
; X32-SSE41-NEXT: movdqa %xmm2, %xmm0
|
||||
; X32-SSE41-NEXT: retl
|
||||
%extmask = sext <4 x i1> %mask to <4 x i64>
|
||||
@ -576,72 +476,35 @@ define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) {
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: pslld $24, %xmm0
|
||||
; SSE2-NEXT: psrad $24, %xmm0
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
|
||||
; SSE2-NEXT: movd %xmm1, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm2
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
||||
; SSE2-NEXT: movd %xmm1, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm1
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; SSE2-NEXT: movd %xmm0, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm1
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSE2-NEXT: movd %xmm0, %rax
|
||||
; SSE2-NEXT: cltq
|
||||
; SSE2-NEXT: movd %rax, %xmm0
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE2-NEXT: movdqa %xmm0, %xmm2
|
||||
; SSE2-NEXT: psrad $31, %xmm2
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
|
||||
; SSE2-NEXT: movdqa %xmm1, %xmm2
|
||||
; SSE2-NEXT: psrad $31, %xmm2
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: sext_4i8_to_4i64:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: pslld $24, %xmm0
|
||||
; SSSE3-NEXT: psrad $24, %xmm0
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
|
||||
; SSSE3-NEXT: movd %xmm1, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm2
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
|
||||
; SSSE3-NEXT: movd %xmm1, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm1
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; SSSE3-NEXT: movd %xmm0, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm1
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSSE3-NEXT: movd %xmm0, %rax
|
||||
; SSSE3-NEXT: cltq
|
||||
; SSSE3-NEXT: movd %rax, %xmm0
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
||||
; SSSE3-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSSE3-NEXT: movdqa %xmm0, %xmm2
|
||||
; SSSE3-NEXT: psrad $31, %xmm2
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
|
||||
; SSSE3-NEXT: movdqa %xmm1, %xmm2
|
||||
; SSSE3-NEXT: psrad $31, %xmm2
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: sext_4i8_to_4i64:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: pslld $24, %xmm0
|
||||
; SSE41-NEXT: psrad $24, %xmm0
|
||||
; SSE41-NEXT: pmovzxdq %xmm0, %xmm1
|
||||
; SSE41-NEXT: pextrq $1, %xmm1, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm3
|
||||
; SSE41-NEXT: movd %xmm1, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm2
|
||||
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
|
||||
; SSE41-NEXT: pextrq $1, %xmm0, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm3
|
||||
; SSE41-NEXT: movd %xmm0, %rax
|
||||
; SSE41-NEXT: cltq
|
||||
; SSE41-NEXT: movd %rax, %xmm1
|
||||
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
|
||||
; SSE41-NEXT: pmovsxdq %xmm0, %xmm2
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; SSE41-NEXT: pmovsxdq %xmm0, %xmm1
|
||||
; SSE41-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
@ -666,20 +529,9 @@ define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) {
|
||||
; X32-SSE41: # BB#0:
|
||||
; X32-SSE41-NEXT: pslld $24, %xmm0
|
||||
; X32-SSE41-NEXT: psrad $24, %xmm0
|
||||
; X32-SSE41-NEXT: pmovzxdq %xmm0, %xmm2
|
||||
; X32-SSE41-NEXT: movd %xmm2, %eax
|
||||
; X32-SSE41-NEXT: sarl $31, %eax
|
||||
; X32-SSE41-NEXT: pextrd $2, %xmm2, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm2
|
||||
; X32-SSE41-NEXT: sarl $31, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm2
|
||||
; X32-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
|
||||
; X32-SSE41-NEXT: movd %xmm1, %eax
|
||||
; X32-SSE41-NEXT: sarl $31, %eax
|
||||
; X32-SSE41-NEXT: pextrd $2, %xmm1, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $1, %eax, %xmm1
|
||||
; X32-SSE41-NEXT: sarl $31, %ecx
|
||||
; X32-SSE41-NEXT: pinsrd $3, %ecx, %xmm1
|
||||
; X32-SSE41-NEXT: pmovsxdq %xmm0, %xmm2
|
||||
; X32-SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; X32-SSE41-NEXT: pmovsxdq %xmm0, %xmm1
|
||||
; X32-SSE41-NEXT: movdqa %xmm2, %xmm0
|
||||
; X32-SSE41-NEXT: retl
|
||||
%extmask = sext <4 x i8> %mask to <4 x i64>
|
||||
|
||||
@ -14,8 +14,8 @@ target triple = "x86_64-apple-macosx"
|
||||
; <rdar://problem/18675020>
|
||||
|
||||
; CHECK-LABEL: test:
|
||||
; CHECK: vmovdqa {{.*#+}} xmm0 = [65535,0,0,65535]
|
||||
; CHECK: vmovdqa {{.*#+}} xmm2 = [65533,124,125,14807]
|
||||
; CHECK: vmovdqa {{.*#+}} xmm1 = [65533,124,125,14807]
|
||||
; CHECK: vmovdqa {{.*#+}} xmm1 = [65535,0,0,65535]
|
||||
; CHECK: ret
|
||||
define void @test(<4 x i16>* %a, <4 x i16>* %b) {
|
||||
body:
|
||||
@ -33,13 +33,14 @@ body:
|
||||
; of the condition.
|
||||
;
|
||||
; CHECK-LABEL: test2:
|
||||
; CHECK: vpslld $31, %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm1
|
||||
; CHECK-NEXT: vpshufd $78, %xmm0, %xmm0 ## xmm0 = xmm0[2,3,0,1]
|
||||
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, [[MASK:%ymm[0-9]+]]
|
||||
; CHECK: vblendvpd [[MASK]]
|
||||
; CHECK: retq
|
||||
; CHECK: vpslld $31, %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpsrad $31, %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm1
|
||||
; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
|
||||
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, [[MASK:%ymm[0-9]+]]
|
||||
; CHECK: vblendvpd [[MASK]]
|
||||
; CHECK: retq
|
||||
define void @test2(double** %call1559, i64 %indvars.iv4198, <4 x i1> %tmp1895) {
|
||||
bb:
|
||||
%arrayidx1928 = getelementptr inbounds double*, double** %call1559, i64 %indvars.iv4198
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user