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Fix PR2850 and PR2863. Only generate movddup for 128-bit SSE vector shuffles.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57210 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-10-06 21:13:08 +00:00
parent 65609f2efa
commit 882cdfde51
2 changed files with 13 additions and 0 deletions
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1
lib/Target/X86/X86ISelLowering.cpp
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@ -3954,6 +3954,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
// Canonicalize movddup shuffles.
if (V2IsUndef && Subtarget->hasSSE2() &&
VT.getSizeInBits() == 128 &&
X86::isMOVDDUPMask(PermMask.getNode()))
return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());

12
test/CodeGen/X86/2008-10-06-MMXISelBug.ll Normal file
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@ -0,0 +1,12 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx,+sse2
; PR2850
@tmp_V2i = common global <2 x i32> zeroinitializer ; <<2 x i32>*> [#uses=2]
define void @f0() nounwind {
entry:
%0 = load <2 x i32>* @tmp_V2i, align 8 ; <<2 x i32>> [#uses=1]
%1 = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer ; <<2 x i32>> [#uses=1]
store <2 x i32> %1, <2 x i32>* @tmp_V2i, align 8
ret void
}