RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-11 05:35:11 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[PowerPC] Generate pre-increment floating-point ld/st instructions

Browse Source 
PowerPC supports pre-increment floating-point load/store instructions, both r+r
and r+i, and we had patterns for them, but they were not marked as legal. Mark
them as legal (and add a test case).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228327 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2015-02-05 18:42:53 +00:00
parent 5e00f0d72d
commit 885b67a5c3
2 changed files with 44 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -88,11 +88,15 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
if (Subtarget.useCRBits()) { if (Subtarget.useCRBits()) {
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);

40
test/CodeGen/PowerPC/flt-preinc.ll Normal file
View File

@ -0,0 +1,40 @@
; RUN: llc -mcpu=ppc64 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readonly
define float @tf(float* nocapture readonly %i, i32 signext %o) #0 {
entry:
%idx.ext = sext i32 %o to i64
%add.ptr = getelementptr inbounds float* %i, i64 %idx.ext
%0 = load float* %add.ptr, align 4
%add.ptr.sum = add nsw i64 %idx.ext, 1
%add.ptr3 = getelementptr inbounds float* %i, i64 %add.ptr.sum
%1 = load float* %add.ptr3, align 4
%add = fadd float %0, %1
ret float %add
; CHECK-LABEL: @tf
; CHECK: lfsux
; CHECK: blr
}
; Function Attrs: nounwind readonly
define double @td(double* nocapture readonly %i, i32 signext %o) #0 {
entry:
%idx.ext = sext i32 %o to i64
%add.ptr = getelementptr inbounds double* %i, i64 %idx.ext
%0 = load double* %add.ptr, align 8
%add.ptr.sum = add nsw i64 %idx.ext, 1
%add.ptr3 = getelementptr inbounds double* %i, i64 %add.ptr.sum
%1 = load double* %add.ptr3, align 8
%add = fadd double %0, %1
ret double %add
; CHECK-LABEL: @td
; CHECK: lfdux
; CHECK: blr
}
attributes #0 = { nounwind readonly }