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Reverting r297821 due to breaking lld test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297838 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sam Parker
parent
302f165b35
commit
8888b5e1c6
@ -257,43 +257,24 @@ public:
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uint64_t Size, uint64_t &Target) const override {
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// We only handle PCRel branches for now.
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if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
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return false;
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int64_t Imm = Inst.getOperand(0).getImm();
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Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
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return true;
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}
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};
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class ThumbMCInstrAnalysis : public ARMMCInstrAnalysis {
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public:
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ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}
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bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
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uint64_t Size, uint64_t &Target) const override {
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// We only handle PCRel branches for now.
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if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
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return false;
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int64_t Imm = Inst.getOperand(0).getImm();
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Target = Addr+Imm+4; // In Thumb mode the PC is always off by 4 bytes.
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return true;
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}
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};
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}
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static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
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return new ARMMCInstrAnalysis(Info);
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}
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static MCInstrAnalysis *createThumbMCInstrAnalysis(const MCInstrInfo *Info) {
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return new ThumbMCInstrAnalysis(Info);
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}
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// Force static initialization.
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extern "C" void LLVMInitializeARMTargetMC() {
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for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
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return false;
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int64_t Imm = Inst.getOperand(0).getImm();
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// FIXME: This is not right for thumb.
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Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
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return true;
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}
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};
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}
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static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
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return new ARMMCInstrAnalysis(Info);
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}
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// Force static initialization.
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extern "C" void LLVMInitializeARMTargetMC() {
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for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
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&getTheThumbLETarget(), &getTheThumbBETarget()}) {
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// Register the MC asm info.
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RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
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@ -305,12 +286,15 @@ extern "C" void LLVMInitializeARMTargetMC() {
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TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(*T,
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ARM_MC::createARMMCSubtargetInfo);
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TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
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TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);
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TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);
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TargetRegistry::RegisterMCSubtargetInfo(*T,
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ARM_MC::createARMMCSubtargetInfo);
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// Register the MC instruction analyzer.
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TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);
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TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
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TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);
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TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);
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// Register the obj target streamer.
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TargetRegistry::RegisterObjectTargetStreamer(*T,
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@ -326,18 +310,12 @@ extern "C" void LLVMInitializeARMTargetMC() {
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TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter);
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// Register the MC relocation info.
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TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);
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}
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// Register the MC instruction analyzer.
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for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget()})
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TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);
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for (Target *T : {&getTheThumbLETarget(), &getTheThumbBETarget()})
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TargetRegistry::RegisterMCInstrAnalysis(*T, createThumbMCInstrAnalysis);
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// Register the MC Code Emitter
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for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()})
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TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);
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TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);
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}
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// Register the MC Code Emitter
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for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()})
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TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);
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for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()})
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TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter);
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@ -1,15 +0,0 @@
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@ RUN: llvm-mc -mcpu=cortex-a9 -triple armv7.arm-none-eabi -filetype obj -o - %s \
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@ RUN: | llvm-objdump -mcpu=cortex-a9 -triple armv7.arm-none-eabi -d - \
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@ RUN: | FileCheck %s -check-prefix CHECK-ARM
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@ RUN: llvm-mc -mcpu=cortex-m3 -triple thumbv7.arm-none-eabi -filetype obj -o - %s \
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@ RUN: | llvm-objdump -mcpu=cortex-m3 -triple thumbv7.arm-none-eabi -d - \
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@ RUN: | FileCheck %s -check-prefix CHECK-THUMB
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b.w .Lbranch
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@ CHECK-ARM: b #4 <$a.0+0xC>
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@ CHECK-THUMB: b.w #8 <$t.0+0xC>
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adds r0, r1, #42
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adds r1, r2, #42
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.Lbranch:
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movs r2, r3
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@ -11,49 +11,49 @@
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.global target
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.thumb_func
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branch24t:
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b target
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@ CHECK-ENCODING-LABEL: branch24t:
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@ CHECK-ENCODING-NEXT: b.w #0
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.thumb_func
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branch20t:
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bcc target
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@ CHECK-ENCODING-LABEL: branch20t:
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@ CHECK-ENCODING-NEXT: blo.w #0
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.thumb_func
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blx23t:
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bl target
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@ CHECK-ENCODING-LABEL: blx23t:
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@ CHECK-ENCODING-NEXT: bl #0
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.thumb_func
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branch24t:
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b target
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@ CHECK-ENCODING-LABEL: branch24t
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@ CHECK-ENCODING-NEXT: b.w #0
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.thumb_func
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branch20t:
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bcc target
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@ CHECK-ENCODING-LABEL: branch20t
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@ CHECK-ENCODING-NEXT: blo.w #0
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.thumb_func
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blx23t:
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bl target
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@ CHECK-ENCODING-LABEL: blx23t
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@ CHECK-ENCODING-NEXT: bl #0
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.thumb_func
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mov32t:
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movw r0, :lower16:target
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movt r0, :upper16:target
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blx r0
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@ CHECK-ENCODING-LABEL: mov32t:
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@ CHECK-ENCODING-NEXT: movw r0, #0
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@ CHECK-ENCODING-NEXT: movt r0, #0
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@ CHECK-ENCODING-NEXT: blx r0
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movt r0, :upper16:target
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blx r0
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@ CHECK-ENCODING-LABEL: mov32t
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@ CHECK-ENCODING-NEXT: movw r0, #0
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@ CHECK-ENCODING-NEXT: movt r0, #0
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@ CHECK-ENCODING-NEXT: blx r0
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.thumb_func
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addr32:
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ldr r0, .Laddr32
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bx r0
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trap
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.Laddr32:
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.long target
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@ CHECK-ENCODING-LABEL: addr32:
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@ CHECK-ENCODING-NEXT: ldr r0, [pc, #4]
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@ CHECK-ENCODING-NEXT: bx r0
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@ CHECK-ENCODING-NEXT: trap
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.Laddr32:
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.long target
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@ CHECK-ENCODING-LABEL: addr32
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@ CHECK-ENCODING-NEXT: ldr r0, [pc, #4]
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@ CHECK-ENCODING-NEXT: bx r0
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@ CHECK-ENCODING-NEXT: trap
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@ CHECK-ENCODING-NEXT: movs r0, r0
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@ CHECK-ENCODING-NEXT: movs r0, r0
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@ -62,13 +62,13 @@ addr32nb:
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ldr r0, .Laddr32nb
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bx r0
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trap
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.Laddr32nb:
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.long target(imgrel)
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@ CHECK-ENCODING-LABEL: addr32nb:
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@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]
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@ CHECK-ENCODING-NEXT: bx r0
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@ CHECK-ENCODING-NEXT: trap
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.Laddr32nb:
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.long target(imgrel)
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@ CHECK-ENCODING-LABEL: addr32nb
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@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]
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@ CHECK-ENCODING-NEXT: bx r0
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@ CHECK-ENCODING-NEXT: trap
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@ CHECK-ENCODING-NEXT: movs r0, r0
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@ CHECK-ENCODING-NEXT: movs r0, r0
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@ -77,13 +77,13 @@ secrel:
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ldr r0, .Lsecrel
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bx r0
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trap
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.Lsecrel:
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.long target(secrel32)
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@ CHECK-ENCODING-LABEL: secrel:
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@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]
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@ CHECK-ENCODING-NEXT: bx r0
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@ CHECK-ENCODING-NEXT: trap
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.Lsecrel:
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.long target(secrel32)
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@ CHECK-ENCODING-LABEL: secrel
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@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]
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@ CHECK-ENCODING-NEXT: bx r0
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@ CHECK-ENCODING-NEXT: trap
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@ CHECK-ENCODING-NEXT: movs r0, r0
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@ CHECK-ENCODING-NEXT: movs r0, r0
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