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- Add encodings for multiply add/subtract instructions in all their glory.
- Add missing patterns for some multiply add/subtract instructions. - Add encodings for VMRS and VMSR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
a5bbde8efd
commit
88cf038436
@ -1595,7 +1595,7 @@ void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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switch(Opcode) {
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switch (Opcode) {
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default:
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llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
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@ -1603,14 +1603,6 @@ void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
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// No further encoding needed.
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break;
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case ARM::VMRS:
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case ARM::VMSR: {
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const MachineOperand &MO0 = MI.getOperand(0);
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// Encode Rt.
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Binary |= getARMRegisterNumbering(MO0.getReg()) << ARMII::RegRdShift;
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break;
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}
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case ARM::FCONSTD:
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case ARM::FCONSTS: {
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// Encode Dd / Sd.
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@ -25,16 +25,16 @@ def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
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def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
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def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
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def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
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def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
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def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag, SDNPOutFlag]>;
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def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
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def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
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def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
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//===----------------------------------------------------------------------===//
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// Operand Definitions.
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//
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def vfp_f32imm : Operand<f32>,
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PatLeaf<(f32 fpimm), [{
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return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
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@ -672,7 +672,7 @@ def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
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def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
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(outs SPR:$Sd), (ins DPR:$Dm),
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IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
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[(set SPR:$Sd, (int_arm_vcvtru (f64 DPR:$Dm)))]> {
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[(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
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let Inst{7} = 0; // Z bit
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}
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@ -735,7 +735,7 @@ def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
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(outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
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IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
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[/* For disassembly only; pattern left blank */]>;
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}
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} // End of 'let isCodeGenOnly = 1 in'
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// Fixed-Point to FP:
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@ -779,7 +779,7 @@ def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
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(outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
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IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
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[/* For disassembly only; pattern left blank */]>;
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}
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} // End of 'let isCodeGenOnly = 1 in'
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} // End of 'let Constraints = "$src = $dst" in'
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@ -787,62 +787,100 @@ def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
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// FP FMA Operations.
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//
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def VMLAD : ADbI_vmlX<0b11100, 0b00, 0, 0,
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(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vmla", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b),
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(f64 DPR:$dstin)))]>,
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RegConstraint<"$dstin = $dst">;
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class ADbI_vmlX_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4,
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dag oops, dag iops, InstrItinClass itin, string opc,
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string asm, list<dag> pattern>
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: ADbI_vmlX<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
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// Instruction operands.
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bits<5> Dd;
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bits<5> Dn;
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bits<5> Dm;
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def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
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(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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IIC_fpMAC32, "vmla", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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// Encode instruction operands.
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let Inst{19-16} = Dn{3-0};
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let Inst{7} = Dn{4};
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let Inst{15-12} = Dd{3-0};
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let Inst{22} = Dd{4};
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let Inst{3-0} = Dm{3-0};
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let Inst{5} = Dm{4};
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}
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def VNMLSD : ADbI_vmlX<0b11100, 0b01, 0, 0,
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(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vnmls", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b),
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(f64 DPR:$dstin)))]>,
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RegConstraint<"$dstin = $dst">;
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def VMLAD : ADbI_vmlX_Encode<0b11100, 0b00, 0, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">;
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def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
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(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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IIC_fpMAC32, "vnmls", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def VMLAS : ASbIn_Encode<0b11100, 0b00, 0, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fadd (fmul SPR:$Sn, SPR:$Sm),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">;
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def VMLSD : ADbI_vmlX<0b11100, 0b00, 1, 0,
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(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vmls", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)),
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(f64 DPR:$dstin)))]>,
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RegConstraint<"$dstin = $dst">;
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def : Pat<(fadd DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
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(VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
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def : Pat<(fadd SPR:$dstin, (fmul SPR:$a, SPR:$b)),
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(VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
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def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
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(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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IIC_fpMAC32, "vmls", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def VMLSD : ADbI_vmlX_Encode<0b11100, 0b00, 1, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">;
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def VMLSS : ASbIn_Encode<0b11100, 0b00, 1, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fadd (fneg (fmul SPR:$Sn, SPR:$Sm)),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">;
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def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
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(VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
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def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
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(VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
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def VNMLAD : ADbI_vmlX<0b11100, 0b01, 1, 0,
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(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vnmla", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)),
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(f64 DPR:$dstin)))]>,
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RegConstraint<"$dstin = $dst">;
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def VNMLAD : ADbI_vmlX_Encode<0b11100, 0b01, 1, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">;
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def VNMLAS : ASbI_Encode<0b11100, 0b01, 1, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fsub (fneg (fmul SPR:$Sn, SPR:$Sm)),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">;
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def : Pat<(fsub (fneg (fmul DPR:$a, (f64 DPR:$b))), DPR:$dstin),
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(VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
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def : Pat<(fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin),
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(VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
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def VNMLSD : ADbI_vmlX_Encode<0b11100, 0b01, 0, 0,
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(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
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IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
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[(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm),
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(f64 DPR:$Ddin)))]>,
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RegConstraint<"$Ddin = $Dd">;
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def VNMLSS : ASbI_Encode<0b11100, 0b01, 0, 0,
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(outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
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IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
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[(set SPR:$Sd, (fsub (fmul SPR:$Sn, SPR:$Sm),
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SPR:$Sdin))]>,
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RegConstraint<"$Sdin = $Sd">;
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def : Pat<(fsub (fmul DPR:$a, (f64 DPR:$b)), DPR:$dstin),
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(VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
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def : Pat<(fsub (fmul SPR:$a, SPR:$b), SPR:$dstin),
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(VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
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def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
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(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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IIC_fpMAC32, "vnmla", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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//===----------------------------------------------------------------------===//
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// FP Conditional moves.
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@ -894,20 +932,34 @@ def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
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// FPSCR <-> GPR (for disassembly only)
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let hasSideEffects = 1, Uses = [FPSCR] in
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def VMRS : VFPAI<(outs GPR:$dst), (ins), VFPMiscFrm, IIC_fpSTAT,
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"vmrs", "\t$dst, fpscr",
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[(set GPR:$dst, (int_arm_get_fpscr))]> {
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def VMRS : VFPAI<(outs GPR:$Rt), (ins), VFPMiscFrm, IIC_fpSTAT,
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"vmrs", "\t$Rt, fpscr",
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[(set GPR:$Rt, (int_arm_get_fpscr))]> {
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// Instruction operand.
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bits<4> Rt;
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// Encode instruction operand.
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let Inst{15-12} = Rt;
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let Inst{27-20} = 0b11101111;
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let Inst{19-16} = 0b0001;
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let Inst{11-8} = 0b1010;
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let Inst{7} = 0;
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let Inst{6-5} = 0b00;
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let Inst{4} = 1;
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let Inst{3-0} = 0b0000;
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}
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let Defs = [FPSCR] in
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def VMSR : VFPAI<(outs), (ins GPR:$src), VFPMiscFrm, IIC_fpSTAT,
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"vmsr", "\tfpscr, $src",
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[(int_arm_set_fpscr GPR:$src)]> {
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[(int_arm_set_fpscr GPR:$src)]> {
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// Instruction operand.
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bits<4> src;
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// Encode instruction operand.
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let Inst{15-12} = src;
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let Inst{27-20} = 0b11101110;
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let Inst{19-16} = 0b0001;
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let Inst{11-8} = 0b1010;
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@ -256,3 +256,97 @@ entry:
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%conv = fptoui float %a to i32
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ret i32 %conv
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}
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define double @f90(double %a, double %b, double %c) nounwind readnone {
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entry:
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; CHECK: f90
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; FIXME: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee]
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%mul = fmul double %a, %b
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%add = fadd double %mul, %c
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ret double %add
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}
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define float @f91(float %a, float %b, float %c) nounwind readnone {
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entry:
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; CHECK: f91
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; CHECK: vmla.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x00,0xee]
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%mul = fmul float %a, %b
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%add = fadd float %mul, %c
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ret float %add
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}
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define double @f94(double %a, double %b, double %c) nounwind readnone {
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entry:
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; CHECK: f94
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; CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee]
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%mul = fmul double %a, %b
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%sub = fsub double %c, %mul
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ret double %sub
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}
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define float @f95(float %a, float %b, float %c) nounwind readnone {
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entry:
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; CHECK: f95
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; CHECK: vmls.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x00,0xee]
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%mul = fmul float %a, %b
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%sub = fsub float %c, %mul
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ret float %sub
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}
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define double @f96(double %a, double %b, double %c) nounwind readnone {
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entry:
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; CHECK: f96
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; CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee]
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%mul = fmul double %a, %b
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%sub = fsub double -0.000000e+00, %mul
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%sub3 = fsub double %sub, %c
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ret double %sub3
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}
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define float @f97(float %a, float %b, float %c) nounwind readnone {
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entry:
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; CHECK: f97
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; CHECK: vnmla.f32 s2, s1, s0 @ encoding: [0xc0,0x1a,0x10,0xee]
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%mul = fmul float %a, %b
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%sub = fsub float -0.000000e+00, %mul
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%sub3 = fsub float %sub, %c
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ret float %sub3
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}
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define double @f92(double %a, double %b, double %c) nounwind readnone {
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entry:
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; CHECK: f92
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; CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee]
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%mul = fmul double %a, %b
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%sub = fsub double %mul, %c
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ret double %sub
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}
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define float @f93(float %a, float %b, float %c) nounwind readnone {
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entry:
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; CHECK: f93
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; CHECK: vnmls.f32 s2, s1, s0 @ encoding: [0x80,0x1a,0x10,0xee]
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%mul = fmul float %a, %b
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%sub = fsub float %mul, %c
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ret float %sub
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}
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define i32 @f100() nounwind readnone {
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entry:
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; CHECK: f100
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; CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
|
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%0 = tail call i32 @llvm.arm.get.fpscr()
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
declare i32 @llvm.arm.get.fpscr() nounwind readnone
|
||||
|
||||
define void @f101(i32 %a) nounwind {
|
||||
entry:
|
||||
; CHECK: f101
|
||||
; CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
|
||||
tail call void @llvm.arm.set.fpscr(i32 %a)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.arm.set.fpscr(i32) nounwind
|
||||
|
||||
Loading…
Reference in New Issue
Block a user