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Various tweaks related to apint codegen. No functionality

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change for non-funky-sized integers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52151 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2008-06-09 15:48:25 +00:00
parent 8a6ccb5f73
commit 893076354a
4 changed files with 8 additions and 4 deletions
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4
include/llvm/CodeGen/ValueTypes.h
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@ -261,6 +261,10 @@ namespace llvm {
(isExtended() && isVector() && getSizeInBits()==128));
}
/// isByteSized - Return true if the bit size is a multiple of 8.
inline bool isByteSized() const {
return (getSizeInBits() & 7) == 0;
}
/// bitsGT - Return true if this has more bits than VT.
inline bool bitsGT(MVT VT) const {

4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -1785,7 +1785,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
// Loading a non-byte sized integer is only valid if the extra bits
// in memory that complete the byte are zero, which is not known here.
// TODO: remove isSimple check when apint codegen support lands.
EVT.isSimple() && EVT.getSizeInBits() == EVT.getStoreSizeInBits() &&
EVT.isSimple() && EVT.isByteSized() &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
MVT PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to add an offset to the pointer to
@ -3181,7 +3181,7 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
// Do not allow folding to a non-byte-sized integer here. These only
// load correctly if the extra bits in memory that complete the byte
// are zero, which is not known here.
VT.getSizeInBits() == VT.getStoreSizeInBits()) {
VT.isByteSized()) {
assert(N0.getValueType().getSizeInBits() > EVTBits &&
"Cannot truncate to larger type!");
LoadSDNode *LN0 = cast<LoadSDNode>(N0);

2
lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
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@ -94,7 +94,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_Constant(SDNode *N) {
MVT VT = N->getValueType(0);
// Zero extend things like i1, sign extend everything else. It shouldn't
// matter in theory which one we pick, but this tends to give better code?
unsigned Opc = VT != MVT::i1 ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
SDOperand(N, 0));
assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");

2
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -250,7 +250,7 @@ void TargetLowering::computeRegisterProperties() {
NumRegistersForVT[MVT::isVoid] = 0;
// Find the largest integer register class.
unsigned LargestIntReg = MVT::i128;
unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
assert(LargestIntReg != MVT::i1 && "No integer registers defined!");