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Roll r127459 back in:

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Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich 2011-03-11 21:52:04 +00:00
parent 53aac15a60
commit 899eaa3569
16 changed files with 31 additions and 17 deletions
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14
lib/Transforms/Scalar/CodeGenPrepare.cpp
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@ -58,6 +58,10 @@ STATISTIC(NumMemoryInsts, "Number of memory instructions whose address "
STATISTIC(NumExtsMoved, "Number of [s|z]ext instructions combined with loads");
STATISTIC(NumExtUses, "Number of uses of [s|z]ext instructions optimized");
static cl::opt<bool> DisableBranchOpts(
"disable-cgp-branch-opts", cl::Hidden, cl::init(false),
cl::desc("Disable branch optimizations in CodeGenPrepare"));
namespace {
class CodeGenPrepare : public FunctionPass {
/// TLI - Keep a pointer of a TargetLowering to consult for determining
@ -130,6 +134,16 @@ bool CodeGenPrepare::runOnFunction(Function &F) {
SunkAddrs.clear();
if (!DisableBranchOpts) {
MadeChange = false;
for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
MadeChange |= ConstantFoldTerminator(BB);
if (MadeChange && DT)
DT->DT->recalculate(F);
EverMadeChange |= MadeChange;
}
return EverMadeChange;
}

2
test/CodeGen/ARM/constants.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm | FileCheck %s
; RUN: llc < %s -march=arm -disable-cgp-branch-opts | FileCheck %s
define i32 @f1() {
; CHECK: f1

2
test/CodeGen/CellSPU/jumptable.ll
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@ -1,4 +1,4 @@
;RUN: llc --march=cellspu %s -o - | FileCheck %s
;RUN: llc --march=cellspu -disable-cgp-branch-opts %s -o - | FileCheck %s
; This is to check that emitting jumptables doesn't crash llc
define i32 @test(i32 %param) {
entry:

2
test/CodeGen/Thumb/dyn-stackalloc.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts | FileCheck %s
%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }

2
test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
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@ -8,7 +8,7 @@ entry:
; CHECK: sub sp, #8
; CHECK: push
; CHECK: add r7, sp, #4
; CHECK: subs r4, r7, #4
; CHECK: sub.w r4, r7, #4
; CHECK: mov sp, r4
; CHECK-NOT: mov sp, r7
; CHECK: add sp, #8

2
test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-cgp-branch-opts | FileCheck %s
%struct.pix_pos = type { i32, i32, i32, i32, i32, i32 }

2
test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
View File

@ -8,7 +8,7 @@ declare void @bar() nounwind optsize
define void @foo() nounwind optsize {
; CHECK: foo:
; CHECK: push
; CHECK: add r7, sp, #4
; CHECK: mov r7, sp
; CHECK: sub sp, #4
entry:
%m.i = alloca %struct.buf*, align 4

2
test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
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@ -6,8 +6,6 @@ entry:
br label %bb5
bb5: ; preds = %bb5, %entry
; CHECK: %bb5
; CHECK: bne
br i1 undef, label %bb5, label %bb.nph
bb.nph: ; preds = %bb5

2
test/CodeGen/X86/2008-04-16-ReMatBug.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=i386-apple-darwin | grep movw | not grep {, %e}
; RUN: llc < %s -mtriple=i386-apple-darwin -disable-cgp-branch-opts | grep movw | not grep {, %e}
%struct.DBC_t = type { i32, i8*, i16, %struct.DBC_t*, i8*, i8*, i8*, i8*, i8*, %struct.DBC_t*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i32*, i8, i16, %struct.DRVOPT*, i16 }
%struct.DRVOPT = type { i16, i32, i8, %struct.DRVOPT* }

2
test/CodeGen/X86/MachineSink-PHIUse.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-appel-darwin -stats |& grep {machine-sink}
; RUN: llc < %s -mtriple=x86_64-appel-darwin -disable-cgp-branch-opts -stats |& grep {machine-sink}
define fastcc void @t() nounwind ssp {
entry:

4
test/CodeGen/X86/personality.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | FileCheck %s -check-prefix=X64
; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s -check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X64
; RUN: llc < %s -mtriple=i386-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X32
; PR1632
define void @_Z1fv() {

2
test/CodeGen/X86/pr3366.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 | grep movzbl
; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | grep movzbl
; PR3366
define void @_ada_c34002a() nounwind {

4
test/CodeGen/X86/sext-i1.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=32
; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=64
; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | FileCheck %s -check-prefix=32
; RUN: llc < %s -march=x86-64 -disable-cgp-branch-opts | FileCheck %s -check-prefix=64
; rdar://7573216
; PR6146

1
test/CodeGen/X86/zext-extract_subreg.ll
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@ -13,6 +13,7 @@ if.end: ; preds = %if.end.i
; CHECK: %if.end
; CHECK: movl (%{{.*}}), [[REG:%[a-z]+]]
; CHECK-NOT: movl [[REG]], [[REG]]
; CHECK-NEXT: testl [[REG]], [[REG]]
; CHECK-NEXT: xorb
%tmp138 = select i1 undef, i32 0, i32 %tmp7.i
%tmp867 = zext i32 %tmp138 to i64

2
test/MC/ARM/simple-encoding.ll
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@ -1,4 +1,4 @@
;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s
;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding -disable-cgp-branch-opts < %s | FileCheck %s
;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests

3
test/Transforms/CodeGenPrepare/basic.ll
View File

@ -14,13 +14,14 @@ entry:
br i1 %1, label %T, label %trap
; CHECK: entry:
; HECK-NEXT: ret i32 4
; CHECK-NEXT: br label %T
trap: ; preds = %0, %entry
tail call void @llvm.trap() noreturn nounwind
unreachable
T:
; CHECK: ret i32 4
ret i32 4
}