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[mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions

Browse Source 
Differential Revision: http://reviews.llvm.org/D13376


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250382 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zlatko Buljan 2015-10-15 08:59:45 +00:00
parent 5262392dd9
commit 89b9248e6d
6 changed files with 59 additions and 14 deletions
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16
lib/Target/Mips/MicroMipsDSPInstrFormats.td
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@ -10,12 +10,13 @@
class MMDSPInst<string opstr = "">
: MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
let InsnPredicates = [HasDSP];
let AdditionalPredicates = [InMicroMips];
string BaseOpcode = opstr;
string Arch = "mmdsp";
let DecoderNamespace = "MicroMips";
}
class POOL32A_3R_FMT<bits<11> op> : MMDSPInst {
class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
bits<5> rd;
bits<5> rs;
bits<5> rt;
@ -26,3 +27,16 @@ class POOL32A_3R_FMT<bits<11> op> : MMDSPInst {
let Inst{15-11} = rd;
let Inst{10-0} = op;
}
class POOL32A_AC2R_FMT<string opstr, bits<8> funct> : MMDSPInst<opstr> {
bits<2> ac;
bits<5> rs;
bits<5> rt;
let Inst{31-26} = 0;
let Inst{25-21} = rt;
let Inst{20-16} = rs;
let Inst{15-14} = ac;
let Inst{13-6} = funct;
let Inst{5-0} = 0b111100;
}

25
lib/Target/Mips/MicroMipsDSPInstrInfo.td
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@ -12,8 +12,27 @@
//===----------------------------------------------------------------------===//
// Instruction encoding.
class ADDU_QB_MM_ENC : POOL32A_3R_FMT<0b00011001101>;
class ADDU_QB_MM_ENC : POOL32A_3R_FMT<"addu.qb", 0b00011001101>;
class DPA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpa.w.ph", 0b00000010>;
class DPAQ_S_W_PH_MM_ENC : POOL32A_AC2R_FMT<"dpaq_s.w.ph", 0b00001010>;
class DPAQ_SA_L_W_MM_ENC : POOL32A_AC2R_FMT<"dpaq_sa.l.w", 0b01001010>;
class DPAQX_S_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpaqx_s.w.ph", 0b10001010>;
class DPAQX_SA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpaqx_sa.w.ph", 0b11001010>;
class DPAU_H_QBL_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbl", 0b10000010>;
class DPAU_H_QBR_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbr", 0b11000010>;
class DPAX_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpax.w.ph", 0b01000010>;
// Instruction defs.
// MIPS DSP Rev 1
def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC, ISA_MICROMIPS;
// microMIPS DSP Rev 1
def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC;
def DPAQ_S_W_PH_MM : DspMMRel, DPAQ_S_W_PH_MM_ENC, DPAQ_S_W_PH_DESC;
def DPAQ_SA_L_W_MM : DspMMRel, DPAQ_SA_L_W_MM_ENC, DPAQ_SA_L_W_DESC;
def DPAU_H_QBL_MM : DspMMRel, DPAU_H_QBL_MM_ENC, DPAU_H_QBL_DESC;
def DPAU_H_QBR_MM : DspMMRel, DPAU_H_QBR_MM_ENC, DPAU_H_QBR_DESC;
// microMIPS DSP Rev 2
def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2;
def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
ISA_DSPR2;
def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
ISA_DSPR2;
def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;

4
lib/Target/Mips/MipsDSPInstrFormats.td
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@ -28,6 +28,10 @@ def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
AssemblerPredicate<"FeatureDSPR3">;
class ISA_DSPR2 {
list<Predicate> InsnPredicates = [HasDSPR2];
}
// Fields.
class Field6<bits<6> val> {
bits<6> V = val;

18
lib/Target/Mips/MipsDSPInstrInfo.td
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@ -263,6 +263,7 @@ class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@ -444,6 +445,7 @@ class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
(OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
string Constraints = "$acin = $ac";
string BaseOpcode = instr_asm;
}
class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@ -1132,13 +1134,13 @@ def MFHI_DSP : MFHI_ENC, MFHI_DESC;
def MFLO_DSP : MFLO_ENC, MFLO_DESC;
def MTHI_DSP : MTHI_ENC, MTHI_DESC;
def MTLO_DSP : MTLO_ENC, MTLO_DESC;
def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
@ -1214,11 +1216,11 @@ def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC;
def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;

5
test/MC/Disassembler/Mips/micromips-dsp/valid.txt
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@ -1,4 +1,7 @@
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
0x00 0xa4 0x18 0xcd # CHECK: addu.qb $3, $4, $5
0x00 0x65 0x42 0xbc # CHECK: dpaq_s.w.ph $ac1, $5, $3
0x00 0x64 0x92 0xbc # CHECK: dpaq_sa.l.w $ac2, $4, $3
0x00 0x83 0x60 0xbc # CHECK: dpau.h.qbl $ac1, $3, $4
0x02 0xb4 0xb0 0xbc # CHECK: dpau.h.qbr $ac2, $20, $21

5
test/MC/Mips/micromips-dsp/valid.s
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@ -2,4 +2,7 @@
.set noat
addu.qb $3, $4, $5 # CHECK: addu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xcd]
dpaq_s.w.ph $ac1, $5, $3 # CHECK: dpaq_s.w.ph $ac1, $5, $3 # encoding: [0x00,0x65,0x42,0xbc]
dpaq_sa.l.w $ac2, $4, $3 # CHECK: dpaq_sa.l.w $ac2, $4, $3 # encoding: [0x00,0x64,0x92,0xbc]
dpau.h.qbl $ac1, $3, $4 # CHECK: dpau.h.qbl $ac1, $3, $4 # encoding: [0x00,0x83,0x60,0xbc]
dpau.h.qbr $ac2, $20, $21 # CHECK: dpau.h.qbr $ac2, $20, $21 # encoding: [0x02,0xb4,0xb0,0xbc]