mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-12 14:17:59 +00:00
Add support for the 'x' constraint.
Part of rdar://9307836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
c3882164cb
commit
89bd71fc53
@ -7483,6 +7483,7 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
|
||||
case 'l': return C_RegisterClass;
|
||||
case 'w': return C_RegisterClass;
|
||||
case 'h': return C_RegisterClass;
|
||||
case 'x': return C_RegisterClass;
|
||||
}
|
||||
} else if (Constraint.size() == 2) {
|
||||
switch (Constraint[0]) {
|
||||
@ -7555,6 +7556,14 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
|
||||
if (VT.getSizeInBits() == 128)
|
||||
return RCPair(0U, ARM::QPRRegisterClass);
|
||||
break;
|
||||
case 'x':
|
||||
if (VT == MVT::f32)
|
||||
return RCPair(0U, ARM::SPR_8RegisterClass);
|
||||
if (VT.getSizeInBits() == 64)
|
||||
return RCPair(0U, ARM::DPR_8RegisterClass);
|
||||
if (VT.getSizeInBits() == 128)
|
||||
return RCPair(0U, ARM::QPR_8RegisterClass);
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (StringRef("{cc}").equals_lower(Constraint))
|
||||
|
@ -58,3 +58,13 @@ entry:
|
||||
call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
; Radar 9307836 & 9119939
|
||||
|
||||
define float @t6(float %y) nounwind {
|
||||
entry:
|
||||
; CHECK: t6
|
||||
; CHECK: flds s15, s0
|
||||
%0 = tail call float asm "flds s15, $0", "=x"() nounwind
|
||||
ret float %0
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user