Fix Thumb2 aliasing complementary instructions taking modified immediates

There are many Thumb instructions which take 12-bit immediates encoded in a special
8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal
to transform an assembly instruction to be able to encode the immediate.

For example: AND and BIC are complementary instructions; one can switch the AND
to a BIC as long as the immediate is complemented. 

The intent is to switch one instruction into its complementary one when the immediate
cannot be encoded in the form requested in the original assembly and when the 
complementary immediate is encodable.

The patch addresses two issues:
1. definition of t2SOImmNot immediate - it has to check that the orignal value is
not encoded naturally
2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand 
rather than the ARM one.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188548 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mihai Popa 2013-08-16 11:55:44 +00:00
parent 19262ee072
commit 8b36f9e431
3 changed files with 14 additions and 6 deletions

View File

@ -4353,16 +4353,16 @@ def : t2InstAlias<"mvn${p} $Rd, $imm",
(t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
// Same for AND <--> BIC
def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
(t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
(t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
(t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
(t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
(t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
(t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : t2InstAlias<"and${s}${p} $Rdn, $imm",
(t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
(t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
pred:$p, cc_out:$s)>;
// Likewise, "add Rd, t2_so_imm_neg" -> sub
def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",

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@ -946,7 +946,8 @@ public:
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return false;
int64_t Value = CE->getValue();
return ARM_AM::getT2SOImmVal(~Value) != -1;
return ARM_AM::getT2SOImmVal(Value) == -1 &&
ARM_AM::getT2SOImmVal(~Value) != -1;
}
bool isT2SOImmNeg() const {
if (!isImm()) return false;

View File

@ -152,12 +152,15 @@ _func:
ands r3, r12, #0xf
and r1, #0xff
and r1, r1, #0xff
and r5, r4, #0xffffffff
ands r1, r9, #0xffffffff
@ CHECK: and r2, r5, #1044480 @ encoding: [0x05,0xf4,0x7f,0x22]
@ CHECK: ands r3, r12, #15 @ encoding: [0x1c,0xf0,0x0f,0x03]
@ CHECK: and r1, r1, #255 @ encoding: [0x01,0xf0,0xff,0x01]
@ CHECK: and r1, r1, #255 @ encoding: [0x01,0xf0,0xff,0x01]
@ CHECK: and r5, r4, #4294967295 @ encoding: [0x04,0xf0,0xff,0x35]
@ CHECK: ands r1, r9, #4294967295 @ encoding: [0x19,0xf0,0xff,0x31]
@------------------------------------------------------------------------------
@ AND (register)
@ -259,6 +262,8 @@ _func:
@ BIC
@------------------------------------------------------------------------------
bic r10, r1, #0xf
bic r5, r2, #0xffffffff
bics r11, r10, #0xffffffff
bic r12, r3, r6
bic r11, r2, r6, lsl #12
bic r8, r4, r1, lsr #11
@ -276,6 +281,8 @@ _func:
bic r12, r6, ror #29
@ CHECK: bic r10, r1, #15 @ encoding: [0x21,0xf0,0x0f,0x0a]
@ CHECK: bic r5, r2, #4294967295 @ encoding: [0x22,0xf0,0xff,0x35]
@ CHECK: bics r11, r10, #4294967295 @ encoding: [0x3a,0xf0,0xff,0x3b]
@ CHECK: bic.w r12, r3, r6 @ encoding: [0x23,0xea,0x06,0x0c]
@ CHECK: bic.w r11, r2, r6, lsl #12 @ encoding: [0x22,0xea,0x06,0x3b]
@ CHECK: bic.w r8, r4, r1, lsr #11 @ encoding: [0x24,0xea,0xd1,0x28]