RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-25 04:39:44 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM movw/movt fixups need to mask the high bits.

Browse Source 
The fixup value comes in as the whole 32-bit value, so for the lo16 fixup,
the upper bits need to be masked off. Previously we assumed the masking had
already been done and asserted.

rdar://9635991

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133818 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-06-24 20:06:59 +00:00
parent 32e7abd080
commit 8b45456700
1 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
lib/Target/ARM/ARMAsmBackend.cpp
View File

@ -174,7 +174,8 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
Value >>= 16;
// Fallthrough
case ARM::fixup_t2_movw_lo16:
case ARM::fixup_t2_movt_hi16_pcrel:
case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
// the other hi16 fixup?
case ARM::fixup_t2_movw_lo16_pcrel: {
unsigned Hi4 = (Value & 0xF000) >> 12;
unsigned i = (Value & 0x800) >> 11;
@ -184,8 +185,10 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
// inst{26} = i;
// inst{14-12} = Mid3;
// inst{7-0} = Lo8;
assert ((((int64_t)Value) >= -0x8000) && (((int64_t)Value) <= 0x7fff) &&
"Out of range pc-relative fixup value!");
// The value comes in as the whole thing, not just the portion required
// for this fixup, so we need to mask off the bits not handled by this
// portion (lo vs. hi).
Value &= 0xffff;
Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
uint64_t swapped = (Value & 0xFFFF0000) >> 16;
swapped |= (Value & 0x0000FFFF) << 16;