diff --git a/lib/Support/Triple.cpp b/lib/Support/Triple.cpp index ec39fd6e748..57d6d2b3cf6 100644 --- a/lib/Support/Triple.cpp +++ b/lib/Support/Triple.cpp @@ -178,7 +178,6 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) { .Case("aarch64", aarch64) .Case("aarch64_be", aarch64_be) .Case("arm64", aarch64) // "arm64" is an alias for "aarch64" - .Case("arm64_be", aarch64_be) // "arm64_be" is an alias for "aarch64_be" .Case("arm", arm) .Case("armeb", armeb) .Case("mips", mips) @@ -251,7 +250,6 @@ static Triple::ArchType parseArch(StringRef ArchName) { .Case("aarch64", Triple::aarch64) .Case("aarch64_be", Triple::aarch64_be) .Case("arm64", Triple::aarch64) - .Case("arm64_be", Triple::aarch64_be) .Cases("arm", "xscale", Triple::arm) // FIXME: It would be good to replace these with explicit names for all the // various suffixes supported. diff --git a/lib/Target/AArch64/AArch64AsmPrinter.cpp b/lib/Target/AArch64/AArch64AsmPrinter.cpp index cd94e244dc3..a1e35a6e2eb 100644 --- a/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -518,7 +518,5 @@ void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) { extern "C" void LLVMInitializeAArch64AsmPrinter() { RegisterAsmPrinter X(TheAArch64leTarget); RegisterAsmPrinter Y(TheAArch64beTarget); - - RegisterAsmPrinter Z(TheARM64leTarget); - RegisterAsmPrinter W(TheARM64beTarget); + RegisterAsmPrinter Z(TheARM64Target); } diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp index f99b90b800f..5e15582d47e 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -63,9 +63,7 @@ extern "C" void LLVMInitializeAArch64Target() { // Register the target. RegisterTargetMachine X(TheAArch64leTarget); RegisterTargetMachine Y(TheAArch64beTarget); - - RegisterTargetMachine Z(TheARM64leTarget); - RegisterTargetMachine W(TheARM64beTarget); + RegisterTargetMachine Z(TheARM64Target); } /// TargetMachine ctor - Create an AArch64 architecture model. diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 37e92961ff0..3ec83db63a6 100644 --- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -4140,9 +4140,7 @@ AArch64AsmParser::classifySymbolRef(const MCExpr *Expr, extern "C" void LLVMInitializeAArch64AsmParser() { RegisterMCAsmParser X(TheAArch64leTarget); RegisterMCAsmParser Y(TheAArch64beTarget); - - RegisterMCAsmParser Z(TheARM64leTarget); - RegisterMCAsmParser W(TheARM64beTarget); + RegisterMCAsmParser Z(TheARM64Target); } #define GET_REGISTER_MATCHER diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 6de27d6d51a..ee5a4c97a3f 100644 --- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -243,13 +243,9 @@ extern "C" void LLVMInitializeAArch64Disassembler() { TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget, createAArch64ExternalSymbolizer); - TargetRegistry::RegisterMCDisassembler(TheARM64leTarget, + TargetRegistry::RegisterMCDisassembler(TheARM64Target, createAArch64Disassembler); - TargetRegistry::RegisterMCDisassembler(TheARM64beTarget, - createAArch64Disassembler); - TargetRegistry::RegisterMCSymbolizer(TheARM64leTarget, - createAArch64ExternalSymbolizer); - TargetRegistry::RegisterMCSymbolizer(TheARM64beTarget, + TargetRegistry::RegisterMCSymbolizer(TheARM64Target, createAArch64ExternalSymbolizer); } diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp index ae698c59f6c..19f532a39df 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -142,17 +142,14 @@ extern "C" void LLVMInitializeAArch64TargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn X(TheAArch64leTarget, createAArch64MCAsmInfo); RegisterMCAsmInfoFn Y(TheAArch64beTarget, createAArch64MCAsmInfo); - RegisterMCAsmInfoFn Z(TheARM64leTarget, createAArch64MCAsmInfo); - RegisterMCAsmInfoFn W(TheARM64beTarget, createAArch64MCAsmInfo); + RegisterMCAsmInfoFn Z(TheARM64Target, createAArch64MCAsmInfo); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(TheAArch64leTarget, createAArch64MCCodeGenInfo); TargetRegistry::RegisterMCCodeGenInfo(TheAArch64beTarget, createAArch64MCCodeGenInfo); - TargetRegistry::RegisterMCCodeGenInfo(TheARM64leTarget, - createAArch64MCCodeGenInfo); - TargetRegistry::RegisterMCCodeGenInfo(TheARM64beTarget, + TargetRegistry::RegisterMCCodeGenInfo(TheARM64Target, createAArch64MCCodeGenInfo); // Register the MC instruction info. @@ -160,9 +157,7 @@ extern "C" void LLVMInitializeAArch64TargetMC() { createAArch64MCInstrInfo); TargetRegistry::RegisterMCInstrInfo(TheAArch64beTarget, createAArch64MCInstrInfo); - TargetRegistry::RegisterMCInstrInfo(TheARM64leTarget, - createAArch64MCInstrInfo); - TargetRegistry::RegisterMCInstrInfo(TheARM64beTarget, + TargetRegistry::RegisterMCInstrInfo(TheARM64Target, createAArch64MCInstrInfo); // Register the MC register info. @@ -170,9 +165,7 @@ extern "C" void LLVMInitializeAArch64TargetMC() { createAArch64MCRegisterInfo); TargetRegistry::RegisterMCRegInfo(TheAArch64beTarget, createAArch64MCRegisterInfo); - TargetRegistry::RegisterMCRegInfo(TheARM64leTarget, - createAArch64MCRegisterInfo); - TargetRegistry::RegisterMCRegInfo(TheARM64beTarget, + TargetRegistry::RegisterMCRegInfo(TheARM64Target, createAArch64MCRegisterInfo); // Register the MC subtarget info. @@ -180,9 +173,7 @@ extern "C" void LLVMInitializeAArch64TargetMC() { createAArch64MCSubtargetInfo); TargetRegistry::RegisterMCSubtargetInfo(TheAArch64beTarget, createAArch64MCSubtargetInfo); - TargetRegistry::RegisterMCSubtargetInfo(TheARM64leTarget, - createAArch64MCSubtargetInfo); - TargetRegistry::RegisterMCSubtargetInfo(TheARM64beTarget, + TargetRegistry::RegisterMCSubtargetInfo(TheARM64Target, createAArch64MCSubtargetInfo); // Register the asm backend. @@ -190,19 +181,15 @@ extern "C" void LLVMInitializeAArch64TargetMC() { createAArch64leAsmBackend); TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget, createAArch64beAsmBackend); - TargetRegistry::RegisterMCAsmBackend(TheARM64leTarget, + TargetRegistry::RegisterMCAsmBackend(TheARM64Target, createAArch64leAsmBackend); - TargetRegistry::RegisterMCAsmBackend(TheARM64beTarget, - createAArch64beAsmBackend); // Register the MC Code Emitter TargetRegistry::RegisterMCCodeEmitter(TheAArch64leTarget, createAArch64MCCodeEmitter); TargetRegistry::RegisterMCCodeEmitter(TheAArch64beTarget, createAArch64MCCodeEmitter); - TargetRegistry::RegisterMCCodeEmitter(TheARM64leTarget, - createAArch64MCCodeEmitter); - TargetRegistry::RegisterMCCodeEmitter(TheARM64beTarget, + TargetRegistry::RegisterMCCodeEmitter(TheARM64Target, createAArch64MCCodeEmitter); // Register the object streamer. @@ -210,16 +197,13 @@ extern "C" void LLVMInitializeAArch64TargetMC() { createMCStreamer); TargetRegistry::RegisterMCObjectStreamer(TheAArch64beTarget, createMCStreamer); - TargetRegistry::RegisterMCObjectStreamer(TheARM64leTarget, createMCStreamer); - TargetRegistry::RegisterMCObjectStreamer(TheARM64beTarget, createMCStreamer); + TargetRegistry::RegisterMCObjectStreamer(TheARM64Target, createMCStreamer); // Register the MCInstPrinter. TargetRegistry::RegisterMCInstPrinter(TheAArch64leTarget, createAArch64MCInstPrinter); TargetRegistry::RegisterMCInstPrinter(TheAArch64beTarget, createAArch64MCInstPrinter); - TargetRegistry::RegisterMCInstPrinter(TheARM64leTarget, - createAArch64MCInstPrinter); - TargetRegistry::RegisterMCInstPrinter(TheARM64beTarget, + TargetRegistry::RegisterMCInstPrinter(TheARM64Target, createAArch64MCInstPrinter); } diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h index d886ea23c13..c2cfc393de6 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -31,8 +31,7 @@ class raw_ostream; extern Target TheAArch64leTarget; extern Target TheAArch64beTarget; -extern Target TheARM64leTarget; -extern Target TheARM64beTarget; +extern Target TheARM64Target; MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, diff --git a/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp b/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp index 94b34a541c3..1fee256c72c 100644 --- a/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp +++ b/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp @@ -14,17 +14,14 @@ using namespace llvm; namespace llvm { Target TheAArch64leTarget; Target TheAArch64beTarget; -Target TheARM64leTarget; -Target TheARM64beTarget; +Target TheARM64Target; } // end namespace llvm extern "C" void LLVMInitializeAArch64TargetInfo() { // Now register the "arm64" name for use with "-march". We don't want it to // take possession of the Triple::aarch64 tag though. RegisterTarget X( - TheARM64leTarget, "arm64", "ARM64 (little endian)"); - RegisterTarget Y( - TheARM64beTarget, "arm64_be", "ARM64 (big endian)"); + TheARM64Target, "arm64", "ARM64 (little endian)"); RegisterTarget Z( TheAArch64leTarget, "aarch64", "AArch64 (little endian)"); diff --git a/test/CodeGen/AArch64/adc.ll b/test/CodeGen/AArch64/adc.ll index 892573ba06b..0488ee2142c 100644 --- a/test/CodeGen/AArch64/adc.ll +++ b/test/CodeGen/AArch64/adc.ll @@ -1,5 +1,5 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s -; RUN: llc -verify-machineinstrs < %s -mtriple=arm64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s define i128 @test_simple(i128 %a, i128 %b, i128 %c) { ; CHECK-LABEL: test_simple: diff --git a/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll b/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll index f0e968b2c17..d2985f4dd66 100644 --- a/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll +++ b/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple arm64_be < %s -aarch64-load-store-opt=false -O1 -o - | FileCheck %s -; RUN: llc -mtriple arm64_be < %s -aarch64-load-store-opt=false -O0 -fast-isel=true -o - | FileCheck %s +; RUN: llc -mtriple aarch64_be < %s -aarch64-load-store-opt=false -O1 -o - | FileCheck %s +; RUN: llc -mtriple aarch64_be < %s -aarch64-load-store-opt=false -O0 -fast-isel=true -o - | FileCheck %s ; CHECK-LABEL: test_i64_f64: define void @test_i64_f64(double* %p, i64* %q) { diff --git a/test/CodeGen/AArch64/arm64-big-endian-eh.ll b/test/CodeGen/AArch64/arm64-big-endian-eh.ll index 93e7da98de2..a51703a8fc4 100644 --- a/test/CodeGen/AArch64/arm64-big-endian-eh.ll +++ b/test/CodeGen/AArch64/arm64-big-endian-eh.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple arm64_be-linux-gnu -filetype obj < %s | llvm-objdump -s - | FileCheck %s +; RUN: llc -mtriple aarch64_be-linux-gnu -filetype obj < %s | llvm-objdump -s - | FileCheck %s ; ARM EHABI for big endian ; This test case checks whether CIE length record is laid out in big endian format. diff --git a/test/CodeGen/AArch64/arm64-big-endian-varargs.ll b/test/CodeGen/AArch64/arm64-big-endian-varargs.ll index d7b26b97523..db1f48c6fd5 100644 --- a/test/CodeGen/AArch64/arm64-big-endian-varargs.ll +++ b/test/CodeGen/AArch64/arm64-big-endian-varargs.ll @@ -3,7 +3,7 @@ ; Vararg saving must save Q registers using the equivalent of STR/STP. target datalayout = "E-m:e-i64:64-i128:128-n32:64-S128" -target triple = "arm64_be-arm-none-eabi" +target triple = "aarch64_be-arm-none-eabi" %struct.__va_list = type { i8*, i8*, i8*, i32, i32 } diff --git a/test/CodeGen/AArch64/arm64-big-endian-vector-callee.ll b/test/CodeGen/AArch64/arm64-big-endian-vector-callee.ll index 1dcccf106a2..cc9badc5c55 100644 --- a/test/CodeGen/AArch64/arm64-big-endian-vector-callee.ll +++ b/test/CodeGen/AArch64/arm64-big-endian-vector-callee.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple arm64_be < %s -aarch64-load-store-opt=false -o - | FileCheck %s -; RUN: llc -mtriple arm64_be < %s -fast-isel=true -aarch64-load-store-opt=false -o - | FileCheck %s +; RUN: llc -mtriple aarch64_be < %s -aarch64-load-store-opt=false -o - | FileCheck %s +; RUN: llc -mtriple aarch64_be < %s -fast-isel=true -aarch64-load-store-opt=false -o - | FileCheck %s ; CHECK-LABEL: test_i64_f64: define i64 @test_i64_f64(double %p) { diff --git a/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll b/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll index 9a12b7a0115..d72d0a5db41 100644 --- a/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll +++ b/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple arm64_be < %s -aarch64-load-store-opt=false -o - | FileCheck %s -; RUN: llc -mtriple arm64_be < %s -aarch64-load-store-opt=false -fast-isel=true -O0 -o - | FileCheck %s +; RUN: llc -mtriple aarch64_be < %s -aarch64-load-store-opt=false -o - | FileCheck %s +; RUN: llc -mtriple aarch64_be < %s -aarch64-load-store-opt=false -fast-isel=true -O0 -o - | FileCheck %s ; CHECK-LABEL: test_i64_f64: declare i64 @test_i64_f64_helper(double %p) diff --git a/test/CodeGen/AArch64/arm64-fast-isel-call.ll b/test/CodeGen/AArch64/arm64-fast-isel-call.ll index 8d756ae5461..caf73bf58a4 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-call.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-call.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64_be-linux-gnu | FileCheck %s --check-prefix=CHECK-BE +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=aarch64_be-linux-gnu | FileCheck %s --check-prefix=CHECK-BE define void @call0() nounwind { entry: diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll index 422c5765ec4..51979f0bbf5 100644 --- a/test/CodeGen/AArch64/func-calls.ll +++ b/test/CodeGen/AArch64/func-calls.ll @@ -1,7 +1,7 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-neon | FileCheck --check-prefix=CHECK-NONEON %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s -; RUN: llc -verify-machineinstrs < %s -mtriple=arm64_be-none-linux-gnu | FileCheck --check-prefix=CHECK-BE %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK-BE %s %myStruct = type { i64 , i8, i32 } diff --git a/test/CodeGen/AArch64/mul-lohi.ll b/test/CodeGen/AArch64/mul-lohi.ll index 0689fbdcc07..550a8cb24b7 100644 --- a/test/CodeGen/AArch64/mul-lohi.ll +++ b/test/CodeGen/AArch64/mul-lohi.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=arm64-apple-ios7.0 %s -o - | FileCheck %s -; RUN: llc -mtriple=arm64_be-linux-gnu %s -o - | FileCheck --check-prefix=CHECK-BE %s +; RUN: llc -mtriple=aarch64_be-linux-gnu %s -o - | FileCheck --check-prefix=CHECK-BE %s define i128 @test_128bitmul(i128 %lhs, i128 %rhs) { ; CHECK-LABEL: test_128bitmul: diff --git a/test/CodeGen/AArch64/pic-eh-stubs.ll b/test/CodeGen/AArch64/pic-eh-stubs.ll index e8c762504fc..93ee0e67b90 100644 --- a/test/CodeGen/AArch64/pic-eh-stubs.ll +++ b/test/CodeGen/AArch64/pic-eh-stubs.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s -; RUN: llc -mtriple=arm64_be-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s +; RUN: llc -mtriple=aarch64_be-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s ; Make sure exception-handling PIC code can be linked correctly. An alternative ; to the sequence described below would have .gcc_except_table itself writable diff --git a/test/MC/AArch64/arm64-be-datalayout.s b/test/MC/AArch64/arm64-be-datalayout.s index f448a4b86e1..a5b48f1c594 100644 --- a/test/MC/AArch64/arm64-be-datalayout.s +++ b/test/MC/AArch64/arm64-be-datalayout.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple arm64_be %s | llvm-readobj -section-data -sections | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple aarch64_be %s | llvm-readobj -section-data -sections | FileCheck %s // CHECK: 0000: 00123456 789ABCDE foo: .xword 0x123456789abcde