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Revert r109079, which broke a lot of CodeGen tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109082 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1036,7 +1036,7 @@ namespace {
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std::vector<SUnit*> Queue;
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SF Picker;
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unsigned CurQueueId;
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bool TracksRegPressure;
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bool isBottomUp;
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protected:
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// SUnits - The SUnits for the current graph.
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@ -1061,22 +1061,20 @@ namespace {
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public:
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RegReductionPriorityQueue(MachineFunction &mf,
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bool tracksrp,
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bool isbottomup,
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const TargetInstrInfo *tii,
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const TargetRegisterInfo *tri,
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const TargetLowering *tli)
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: Picker(this), CurQueueId(0), TracksRegPressure(tracksrp),
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: Picker(this), CurQueueId(0), isBottomUp(isbottomup),
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MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) {
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if (TracksRegPressure) {
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unsigned NumRC = TRI->getNumRegClasses();
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RegLimit.resize(NumRC);
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RegPressure.resize(NumRC);
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std::fill(RegLimit.begin(), RegLimit.end(), 0);
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std::fill(RegPressure.begin(), RegPressure.end(), 0);
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for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
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E = TRI->regclass_end(); I != E; ++I)
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RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1;
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}
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unsigned NumRC = TRI->getNumRegClasses();
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RegLimit.resize(NumRC);
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RegPressure.resize(NumRC);
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std::fill(RegLimit.begin(), RegLimit.end(), 0);
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std::fill(RegPressure.begin(), RegPressure.end(), 0);
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for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
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E = TRI->regclass_end(); I != E; ++I)
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RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1;
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}
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void initNodes(std::vector<SUnit> &sunits) {
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@ -1209,10 +1207,7 @@ namespace {
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return false;
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}
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void ScheduledNode(SUnit *SU) {
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if (!TracksRegPressure)
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return;
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void OpenPredLives(SUnit *SU) {
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const SDNode *N = SU->getNode();
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if (!N->isMachineOpcode())
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return;
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@ -1265,14 +1260,9 @@ namespace {
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else
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RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
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}
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dumpRegPressure();
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}
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void UnscheduledNode(SUnit *SU) {
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if (!TracksRegPressure)
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return;
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void ClosePredLives(SUnit *SU) {
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const SDNode *N = SU->getNode();
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if (!N->isMachineOpcode())
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return;
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@ -1327,7 +1317,19 @@ namespace {
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
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}
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}
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void ScheduledNode(SUnit *SU) {
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if (!TLI || !isBottomUp)
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return;
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OpenPredLives(SU);
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dumpRegPressure();
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}
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void UnscheduledNode(SUnit *SU) {
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if (!TLI || !isBottomUp)
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return;
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ClosePredLives(SU);
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dumpRegPressure();
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}
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@ -1849,7 +1851,7 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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BURegReductionPriorityQueue *PQ =
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new BURegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
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new BURegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0);
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ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
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PQ->setScheduleDAG(SD);
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return SD;
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@ -1875,7 +1877,7 @@ llvm::createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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SrcRegReductionPriorityQueue *PQ =
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new SrcRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
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new SrcRegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0);
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ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
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PQ->setScheduleDAG(SD);
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return SD;
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