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Revert r109079, which broke a lot of CodeGen tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109082 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2010-07-22 06:01:28 +00:00
parent 214e46eac7
commit 8b9177aee2
1 changed files with 27 additions and 25 deletions
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52
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -1036,7 +1036,7 @@ namespace {
std::vector<SUnit*> Queue; std::vector<SUnit*> Queue;
SF Picker; SF Picker;
unsigned CurQueueId; unsigned CurQueueId;
bool TracksRegPressure; bool isBottomUp;
protected: protected:
// SUnits - The SUnits for the current graph. // SUnits - The SUnits for the current graph.
@ -1061,22 +1061,20 @@ namespace {
public: public:
RegReductionPriorityQueue(MachineFunction &mf, RegReductionPriorityQueue(MachineFunction &mf,
bool tracksrp, bool isbottomup,
const TargetInstrInfo *tii, const TargetInstrInfo *tii,
const TargetRegisterInfo *tri, const TargetRegisterInfo *tri,
const TargetLowering *tli) const TargetLowering *tli)
: Picker(this), CurQueueId(0), TracksRegPressure(tracksrp), : Picker(this), CurQueueId(0), isBottomUp(isbottomup),
MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) { MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) {
if (TracksRegPressure) { unsigned NumRC = TRI->getNumRegClasses();
unsigned NumRC = TRI->getNumRegClasses(); RegLimit.resize(NumRC);
RegLimit.resize(NumRC); RegPressure.resize(NumRC);
RegPressure.resize(NumRC); std::fill(RegLimit.begin(), RegLimit.end(), 0);
std::fill(RegLimit.begin(), RegLimit.end(), 0); std::fill(RegPressure.begin(), RegPressure.end(), 0);
std::fill(RegPressure.begin(), RegPressure.end(), 0); for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), E = TRI->regclass_end(); I != E; ++I)
E = TRI->regclass_end(); I != E; ++I) RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1;
RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1;
}
} }
void initNodes(std::vector<SUnit> &sunits) { void initNodes(std::vector<SUnit> &sunits) {
@ -1209,10 +1207,7 @@ namespace {
return false; return false;
} }
void ScheduledNode(SUnit *SU) { void OpenPredLives(SUnit *SU) {
if (!TracksRegPressure)
return;
const SDNode *N = SU->getNode(); const SDNode *N = SU->getNode();
if (!N->isMachineOpcode()) if (!N->isMachineOpcode())
return; return;
@ -1265,14 +1260,9 @@ namespace {
else else
RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT); RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
} }
dumpRegPressure();
} }
void UnscheduledNode(SUnit *SU) { void ClosePredLives(SUnit *SU) {
if (!TracksRegPressure)
return;
const SDNode *N = SU->getNode(); const SDNode *N = SU->getNode();
if (!N->isMachineOpcode()) if (!N->isMachineOpcode())
return; return;
@ -1327,7 +1317,19 @@ namespace {
unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
RegPressure[RCId] += TLI->getRepRegClassCostFor(VT); RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
} }
}
void ScheduledNode(SUnit *SU) {
if (!TLI || !isBottomUp)
return;
OpenPredLives(SU);
dumpRegPressure();
}
void UnscheduledNode(SUnit *SU) {
if (!TLI || !isBottomUp)
return;
ClosePredLives(SU);
dumpRegPressure(); dumpRegPressure();
} }
@ -1849,7 +1851,7 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
const TargetRegisterInfo *TRI = TM.getRegisterInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo();
BURegReductionPriorityQueue *PQ = BURegReductionPriorityQueue *PQ =
new BURegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0); new BURegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0);
ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ); ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
PQ->setScheduleDAG(SD); PQ->setScheduleDAG(SD);
return SD; return SD;
@ -1875,7 +1877,7 @@ llvm::createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
const TargetRegisterInfo *TRI = TM.getRegisterInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo();
SrcRegReductionPriorityQueue *PQ = SrcRegReductionPriorityQueue *PQ =
new SrcRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0); new SrcRegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0);
ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ); ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
PQ->setScheduleDAG(SD); PQ->setScheduleDAG(SD);
return SD; return SD;