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[mips] Fix test mips64fpldst.ll with machine verifier enabled
Removed micro mips register classes for gp initialization because gp initialization uses pure mips64 instruction. Even when compiling for micro mips, gp initialization can be done with pure mips64 instructions. Reviewed by Simon Dardis Differential: D32286 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301394 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sagar Thakur
parent
78f951e836
commit
8bc6721525
@ -40,11 +40,7 @@ unsigned MipsFunctionInfo::getGlobalBaseReg() {
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const TargetRegisterClass *RC =
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STI.inMips16Mode()
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? &Mips::CPU16RegsRegClass
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: STI.inMicroMipsMode()
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? STI.hasMips64()
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? &Mips::GPRMM16_64RegClass
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: &Mips::GPRMM16RegClass
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: static_cast<const MipsTargetMachine &>(MF.getTarget())
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: static_cast<const MipsTargetMachine &>(MF.getTarget())
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.getABI()
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.IsN64()
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? &Mips::GPR64RegClass
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@ -268,7 +268,7 @@ entry:
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; MM64R6: daddu $2, $[[T1]], $[[T0]]
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; MM64R6-DAG: dmul $3, $5, $7
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; MM32: lw $25, %call16(__multi3)($16)
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; MM32: lw $25, %call16(__multi3)($gp)
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%r = mul i128 %a, %b
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ret i128 %r
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@ -172,7 +172,7 @@ entry:
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; 64R6: ddiv $2, $4, $5
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; 64R6: teq $5, $zero, 7
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; MM32: lw $25, %call16(__divdi3)($2)
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; MM32: lw $25, %call16(__divdi3)($gp)
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; MM64: ddiv $2, $4, $5
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; MM64: teq $5, $zero, 7
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@ -184,15 +184,7 @@ entry:
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define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
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entry:
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; ALL-LABEL: sdiv_i128:
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; GP32: lw $25, %call16(__divti3)($gp)
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; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
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; 64R6: ld $25, %call16(__divti3)($gp)
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; MM32: lw $25, %call16(__divti3)($16)
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; MM64: ld $25, %call16(__divti3)($2)
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; ALL: l{{w|d}} $25, %call16(__divti3)($gp)
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%r = sdiv i128 %a, %b
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ret i128 %r
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@ -164,7 +164,7 @@ entry:
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; 64R6: dmod $2, $4, $5
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; 64R6: teq $5, $zero, 7
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; MM32: lw $25, %call16(__moddi3)($2)
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; MM32: lw $25, %call16(__moddi3)($gp)
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; MM64: dmod $2, $4, $5
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; MM64: teq $5, $zero, 7
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@ -177,14 +177,7 @@ define signext i128 @srem_i128(i128 signext %a, i128 signext %b) {
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entry:
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; ALL-LABEL: srem_i128:
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; GP32: lw $25, %call16(__modti3)($gp)
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; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
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; 64R6: ld $25, %call16(__modti3)($gp)
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; MM32: lw $25, %call16(__modti3)($16)
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; MM64: ld $25, %call16(__modti3)($2)
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; ALL: l{{w|d}} $25, %call16(__modti3)($gp)
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%r = srem i128 %a, %b
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ret i128 %r
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@ -134,7 +134,7 @@ entry:
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; 64R6: ddivu $2, $4, $5
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; 64R6: teq $5, $zero, 7
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; MM32: lw $25, %call16(__udivdi3)($2)
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; MM32: lw $25, %call16(__udivdi3)($gp)
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; MM64: ddivu $2, $4, $5
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; MM64: teq $5, $zero, 7
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@ -147,14 +147,7 @@ define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
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entry:
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; ALL-LABEL: udiv_i128:
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; GP32: lw $25, %call16(__udivti3)($gp)
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; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
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; 64-R6: ld $25, %call16(__udivti3)($gp)
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; MM32: lw $25, %call16(__udivti3)($16)
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; MM64: ld $25, %call16(__udivti3)($2)
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; ALL: l{{w|d}} $25, %call16(__udivti3)($gp)
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%r = udiv i128 %a, %b
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ret i128 %r
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@ -190,7 +190,7 @@ entry:
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; 64R6: dmodu $2, $4, $5
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; 64R6: teq $5, $zero, 7
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; MM32: lw $25, %call16(__umoddi3)($2)
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; MM32: lw $25, %call16(__umoddi3)($gp)
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; MM64: dmodu $2, $4, $5
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; MM64: teq $5, $zero, 7
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@ -208,9 +208,9 @@ entry:
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; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
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; 64R6: ld $25, %call16(__umodti3)($gp)
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; MM32: lw $25, %call16(__umodti3)($16)
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; MM32: lw $25, %call16(__umodti3)($gp)
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; MM64: ld $25, %call16(__umodti3)($2)
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; MM64: ld $25, %call16(__umodti3)($gp)
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%r = urem i128 %a, %b
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ret i128 %r
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@ -14,5 +14,5 @@ entry:
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; Function Attrs: noreturn
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declare void @exit(i32 signext)
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; CHECK: move $gp, ${{[0-9]+}}
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; CHECK: addu $gp, ${{[0-9]+}}
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@ -1,9 +1,9 @@
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; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
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; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
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; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
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; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
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; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64
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; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32
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; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32
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; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64
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@f0 = common global float 0.000000e+00, align 4
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@d0 = common global double 0.000000e+00, align 8
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@ -176,7 +176,7 @@ entry:
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; ALL-LABEL: caller8_1:
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; PIC32: jalr $25
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; PIC32R6: jalr $25
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; PIC32MM: jalr $25
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; PIC32MM: jalr{{.*}} $25
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; STATIC32: jal
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; PIC64: jalr $25
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; STATIC64: jal
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@ -288,7 +288,7 @@ entry:
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; ALL-LABEL: caller13:
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; PIC32: jalr $25
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; PIC32R6: jalr $25
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; PIC32MM: jalr $25
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; PIC32MM: jalr{{.*}} $25
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; STATIC32: jal
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; STATIC64: jal
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; PIC64R6: jalr $25
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