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Make PPCSelectionDAGInfo take a DataLayout instead of a TargetMachine

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since that's all it needs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210853 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2014-06-12 22:56:48 +00:00
parent a7159144c2
commit 8c5dc520ef
3 changed files with 6 additions and 7 deletions
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8
lib/Target/PowerPC/PPCSelectionDAGInfo.cpp
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@ -16,9 +16,7 @@ using namespace llvm;
#define DEBUG_TYPE "powerpc-selectiondag-info" #define DEBUG_TYPE "powerpc-selectiondag-info"
PPCSelectionDAGInfo::PPCSelectionDAGInfo(const PPCTargetMachine &TM) PPCSelectionDAGInfo::PPCSelectionDAGInfo(const DataLayout *DL)
: TargetSelectionDAGInfo(TM.getDataLayout()) { : TargetSelectionDAGInfo(DL) {}
}
PPCSelectionDAGInfo::~PPCSelectionDAGInfo() { PPCSelectionDAGInfo::~PPCSelectionDAGInfo() {}
}

2
lib/Target/PowerPC/PPCSelectionDAGInfo.h
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@ -22,7 +22,7 @@ class PPCTargetMachine;
class PPCSelectionDAGInfo : public TargetSelectionDAGInfo { class PPCSelectionDAGInfo : public TargetSelectionDAGInfo {
public: public:
explicit PPCSelectionDAGInfo(const PPCTargetMachine &TM); explicit PPCSelectionDAGInfo(const DataLayout *DL);
~PPCSelectionDAGInfo(); ~PPCSelectionDAGInfo();
}; };

3
lib/Target/PowerPC/PPCTargetMachine.cpp
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@ -42,7 +42,8 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64Bit) CodeGenOpt::Level OL, bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, *this, is64Bit, OL), TSInfo(*this) { Subtarget(TT, CPU, FS, *this, is64Bit, OL),
TSInfo(Subtarget.getDataLayout()) {
initAsmInfo(); initAsmInfo();
} }