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Provide proper patterns for and with imm instructions. Tune the tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75979 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
25af73303f
commit
8c993e1632
@ -61,224 +61,8 @@ def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
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def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
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def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff.
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//===----------------------------------------------------------------------===//
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// SystemZ specific condition code. These correspond to CondCode in
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// SystemZ.h. They must be kept in synch.
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def SYSTEMZ_COND_E : PatLeaf<(i8 0)>;
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def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>;
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def SYSTEMZ_COND_H : PatLeaf<(i8 2)>;
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def SYSTEMZ_COND_L : PatLeaf<(i8 3)>;
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def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>;
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def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>;
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def LL16 : SDNodeXForm<imm, [{
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// Transformation function: return low 16 bits.
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return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL);
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}]>;
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def LH16 : SDNodeXForm<imm, [{
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// Transformation function: return bits 16-31.
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return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16);
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}]>;
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def HL16 : SDNodeXForm<imm, [{
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// Transformation function: return bits 32-47.
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return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32);
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}]>;
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def HH16 : SDNodeXForm<imm, [{
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// Transformation function: return bits 48-63.
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return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
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}]>;
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def LO32 : SDNodeXForm<imm, [{
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// Transformation function: return low 32 bits.
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return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL);
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}]>;
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def HI32 : SDNodeXForm<imm, [{
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// Transformation function: return bits 32-63.
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return getI32Imm(N->getZExtValue() >> 32);
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}]>;
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def i32ll16 : PatLeaf<(i32 imm), [{
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// i32ll16 predicate - true if the 32-bit immediate has only rightmost 16
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// bits set.
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return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
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}], LL16>;
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def i32lh16 : PatLeaf<(i32 imm), [{
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// i32lh16 predicate - true if the 32-bit immediate has only bits 16-31 set.
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return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
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}], LH16>;
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def i64ll16 : PatLeaf<(imm), [{
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// i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
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// bits set.
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return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
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}], LL16>;
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def i64lh16 : PatLeaf<(imm), [{
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// i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set.
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return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
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}], LH16>;
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def i64hl16 : PatLeaf<(i64 imm), [{
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// i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set.
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return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue());
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}], HL16>;
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def i64hh16 : PatLeaf<(i64 imm), [{
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// i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set.
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return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue());
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}], HH16>;
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def immSExt16 : PatLeaf<(imm), [{
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// immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
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// field.
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if (N->getValueType(0) == MVT::i64) {
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uint64_t val = N->getZExtValue();
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return ((int64_t)val == (int16_t)val);
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} else if (N->getValueType(0) == MVT::i32) {
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uint32_t val = N->getZExtValue();
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return ((int32_t)val == (int16_t)val);
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}
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return false;
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}]>;
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def immSExt32 : PatLeaf<(i64 imm), [{
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// immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
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// field.
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uint64_t val = N->getZExtValue();
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return ((int64_t)val == (int32_t)val);
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}]>;
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def i64lo32 : PatLeaf<(i64 imm), [{
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// i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
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// bits set.
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return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue());
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}], LO32>;
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def i64hi32 : PatLeaf<(i64 imm), [{
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// i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
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return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
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}], HI32>;
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def i32immSExt8 : PatLeaf<(i32 imm), [{
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// i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
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// sign extended field.
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return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
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}]>;
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def i32immSExt16 : PatLeaf<(i32 imm), [{
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// i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit
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// sign extended field.
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return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue();
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}]>;
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def i64immSExt32 : PatLeaf<(i64 imm), [{
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// i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// sign extended field.
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return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
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}]>;
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def i64immZExt32 : PatLeaf<(i64 imm), [{
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// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// zero extended field.
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return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
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}]>;
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// extloads
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def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
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def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
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def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
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def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
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def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
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def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
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def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
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def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
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def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
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def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
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def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
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def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
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def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
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def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
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def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
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// A couple of more descriptive operand definitions.
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// 32-bits but only 8 bits are significant.
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def i32i8imm : Operand<i32>;
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// 32-bits but only 16 bits are significant.
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def i32i16imm : Operand<i32>;
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// 64-bits but only 32 bits are significant.
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def i64i32imm : Operand<i64>;
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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// Unigned i12
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def u12imm : Operand<i32> {
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let PrintMethod = "printU16ImmOperand";
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}
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// Signed i16
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def s16imm : Operand<i32> {
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let PrintMethod = "printS16ImmOperand";
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}
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def s16imm64 : Operand<i64> {
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let PrintMethod = "printS16ImmOperand";
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}
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// Signed i20
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def s20imm : Operand<i32> {
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let PrintMethod = "printS20ImmOperand";
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}
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def s20imm64 : Operand<i64> {
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let PrintMethod = "printS20ImmOperand";
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}
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// Signed i32
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def s32imm : Operand<i32> {
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let PrintMethod = "printS32ImmOperand";
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}
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def s32imm64 : Operand<i64> {
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let PrintMethod = "printS32ImmOperand";
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}
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//===----------------------------------------------------------------------===//
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// SystemZ Operand Definitions.
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//===----------------------------------------------------------------------===//
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// Address operands
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// riaddr := reg + imm
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def riaddr32 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrRI32", []> {
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let PrintMethod = "printRIAddrOperand";
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let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp);
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}
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def riaddr : Operand<i64>,
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ComplexPattern<i64, 2, "SelectAddrRI", []> {
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let PrintMethod = "printRIAddrOperand";
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let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp);
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}
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//===----------------------------------------------------------------------===//
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// rriaddr := reg + reg + imm
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def rriaddr : Operand<i64>,
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ComplexPattern<i64, 3, "SelectAddrRRI", [], []> {
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let PrintMethod = "printRRIAddrOperand";
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let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
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}
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def laaddr : Operand<i64>,
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ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> {
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let PrintMethod = "printRRIAddrOperand";
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let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
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}
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include "SystemZOperands.td"
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//===----------------------------------------------------------------------===//
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// Instruction list..
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@ -602,38 +386,36 @@ def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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// FIXME: Provide proper encoding!
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// FIXME: Compute masked bits properly!
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/*
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def AND32rill16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"nill\t{$dst, $src2}",
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[(set GR32:$dst, (and GR32:$src1, i32ll16:$src2))]>;
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[(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
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def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"nill\t{$dst, $src2}",
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[(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>;
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[(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
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def AND32rilh16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"nilh\t{$dst, $src2}",
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[(set GR32:$dst, (and GR32:$src1, i32lh16:$src2))]>;
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[(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
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def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"nilh\t{$dst, $src2}",
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[(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>;
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[(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
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def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"nihl\t{$dst, $src2}",
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[(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>;
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[(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
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def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"nihh\t{$dst, $src2}",
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[(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>;
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*/
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[(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
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def AND32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"nilf\t{$dst, $src2}",
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[(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
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/*def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"nilf\t{$dst, $src2}",
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[(set GR64:$dst, (and GR64:$src1, i64lo32:$src2))]>;
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[(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
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def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"nihf\t{$dst, $src2}",
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[(set GR64:$dst, (and GR64:$src1, i64hi32:$src2))]>;
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*/
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[(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
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let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
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// FIXME: Provide proper encoding!
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@ -645,12 +427,12 @@ def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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[(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
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}
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def OR32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
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def OR32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"oill\t{$dst, $src2}",
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[(set GR32:$dst, (or GR32:$src1, i64ll16:$src2))]>;
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def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
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[(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
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def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"oilh\t{$dst, $src2}",
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[(set GR32:$dst, (or GR32:$src1, i64lh16:$src2))]>;
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[(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
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def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"oilf\t{$dst, $src2}",
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[(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
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@ -698,14 +480,6 @@ def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"xilf\t{$dst, $src2}",
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[(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
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// FIXME: these 2 instructions seem to require extimm facility
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def XOR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"xilf\t{$dst, $src2}",
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[(set GR64:$dst, (xor GR64:$src1, i64lo32:$src2))]>;
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def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"xihf\t{$dst, $src2}",
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[(set GR64:$dst, (xor GR64:$src1, i64hi32:$src2))]>;
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} // Defs = [PSW]
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let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
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274
lib/Target/SystemZ/SystemZOperands.td
Normal file
274
lib/Target/SystemZ/SystemZOperands.td
Normal file
@ -0,0 +1,274 @@
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//=====- SystemZOperands.td - SystemZ Operands defs ---------*- tblgen-*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the various SystemZ instruction operands.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff.
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//===----------------------------------------------------------------------===//
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// SystemZ specific condition code. These correspond to CondCode in
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// SystemZ.h. They must be kept in synch.
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def SYSTEMZ_COND_E : PatLeaf<(i8 0)>;
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def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>;
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def SYSTEMZ_COND_H : PatLeaf<(i8 2)>;
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def SYSTEMZ_COND_L : PatLeaf<(i8 3)>;
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def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>;
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def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>;
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def LL16 : SDNodeXForm<imm, [{
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// Transformation function: return low 16 bits.
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return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL);
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}]>;
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def LH16 : SDNodeXForm<imm, [{
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// Transformation function: return bits 16-31.
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return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16);
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}]>;
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def HL16 : SDNodeXForm<imm, [{
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// Transformation function: return bits 32-47.
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return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32);
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}]>;
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def HH16 : SDNodeXForm<imm, [{
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// Transformation function: return bits 48-63.
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return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
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}]>;
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def LO32 : SDNodeXForm<imm, [{
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// Transformation function: return low 32 bits.
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return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL);
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}]>;
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def HI32 : SDNodeXForm<imm, [{
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// Transformation function: return bits 32-63.
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return getI32Imm(N->getZExtValue() >> 32);
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}]>;
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|
||||
def i32ll16 : PatLeaf<(i32 imm), [{
|
||||
// i32ll16 predicate - true if the 32-bit immediate has only rightmost 16
|
||||
// bits set.
|
||||
return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
|
||||
}], LL16>;
|
||||
|
||||
def i32lh16 : PatLeaf<(i32 imm), [{
|
||||
// i32lh16 predicate - true if the 32-bit immediate has only bits 16-31 set.
|
||||
return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
|
||||
}], LH16>;
|
||||
|
||||
def i32ll16c : PatLeaf<(i32 imm), [{
|
||||
// i32ll16c predicate - true if the 32-bit immediate has all bits 16-31 set.
|
||||
return ((N->getZExtValue() | 0x00000000FFFF0000ULL) == N->getZExtValue());
|
||||
}], LL16>;
|
||||
|
||||
def i32lh16c : PatLeaf<(i32 imm), [{
|
||||
// i32lh16c predicate - true if the 32-bit immediate has all rightmost 16
|
||||
// bits set.
|
||||
return ((N->getZExtValue() | 0x000000000000FFFFULL) == N->getZExtValue());
|
||||
}], LH16>;
|
||||
|
||||
def i64ll16 : PatLeaf<(i64 imm), [{
|
||||
// i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
|
||||
// bits set.
|
||||
return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
|
||||
}], LL16>;
|
||||
|
||||
def i64lh16 : PatLeaf<(i64 imm), [{
|
||||
// i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set.
|
||||
return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
|
||||
}], LH16>;
|
||||
|
||||
def i64hl16 : PatLeaf<(i64 imm), [{
|
||||
// i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set.
|
||||
return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue());
|
||||
}], HL16>;
|
||||
|
||||
def i64hh16 : PatLeaf<(i64 imm), [{
|
||||
// i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set.
|
||||
return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue());
|
||||
}], HH16>;
|
||||
|
||||
def i64ll16c : PatLeaf<(i64 imm), [{
|
||||
// i64ll16c predicate - true if the 64-bit immediate has only rightmost 16
|
||||
// bits set.
|
||||
return ((N->getZExtValue() | 0xFFFFFFFFFFFF0000ULL) == N->getZExtValue());
|
||||
}], LL16>;
|
||||
|
||||
def i64lh16c : PatLeaf<(i64 imm), [{
|
||||
// i64lh16c predicate - true if the 64-bit immediate has only bits 16-31 set.
|
||||
return ((N->getZExtValue() | 0xFFFFFFFF0000FFFFULL) == N->getZExtValue());
|
||||
}], LH16>;
|
||||
|
||||
def i64hl16c : PatLeaf<(i64 imm), [{
|
||||
// i64hl16c predicate - true if the 64-bit immediate has only bits 32-47 set.
|
||||
return ((N->getZExtValue() | 0xFFFF0000FFFFFFFFULL) == N->getZExtValue());
|
||||
}], HL16>;
|
||||
|
||||
def i64hh16c : PatLeaf<(i64 imm), [{
|
||||
// i64hh16c predicate - true if the 64-bit immediate has only bits 48-63 set.
|
||||
return ((N->getZExtValue() | 0x0000FFFFFFFFFFFFULL) == N->getZExtValue());
|
||||
}], HH16>;
|
||||
|
||||
def immSExt16 : PatLeaf<(imm), [{
|
||||
// immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
|
||||
// field.
|
||||
if (N->getValueType(0) == MVT::i64) {
|
||||
uint64_t val = N->getZExtValue();
|
||||
return ((int64_t)val == (int16_t)val);
|
||||
} else if (N->getValueType(0) == MVT::i32) {
|
||||
uint32_t val = N->getZExtValue();
|
||||
return ((int32_t)val == (int16_t)val);
|
||||
}
|
||||
|
||||
return false;
|
||||
}]>;
|
||||
|
||||
def immSExt32 : PatLeaf<(i64 imm), [{
|
||||
// immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
|
||||
// field.
|
||||
uint64_t val = N->getZExtValue();
|
||||
return ((int64_t)val == (int32_t)val);
|
||||
}]>;
|
||||
|
||||
def i64lo32 : PatLeaf<(i64 imm), [{
|
||||
// i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
|
||||
// bits set.
|
||||
return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue());
|
||||
}], LO32>;
|
||||
|
||||
def i64hi32 : PatLeaf<(i64 imm), [{
|
||||
// i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
|
||||
return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
|
||||
}], HI32>;
|
||||
|
||||
def i64lo32c : PatLeaf<(i64 imm), [{
|
||||
// i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
|
||||
// bits set.
|
||||
return ((N->getZExtValue() | 0xFFFFFFFF00000000ULL) == N->getZExtValue());
|
||||
}], LO32>;
|
||||
|
||||
def i64hi32c : PatLeaf<(i64 imm), [{
|
||||
// i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
|
||||
return ((N->getZExtValue() | 0x00000000FFFFFFFFULL) == N->getZExtValue());
|
||||
}], HI32>;
|
||||
|
||||
def i32immSExt8 : PatLeaf<(i32 imm), [{
|
||||
// i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
|
||||
// sign extended field.
|
||||
return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
|
||||
}]>;
|
||||
|
||||
def i32immSExt16 : PatLeaf<(i32 imm), [{
|
||||
// i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit
|
||||
// sign extended field.
|
||||
return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue();
|
||||
}]>;
|
||||
|
||||
def i64immSExt32 : PatLeaf<(i64 imm), [{
|
||||
// i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
|
||||
// sign extended field.
|
||||
return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
|
||||
}]>;
|
||||
|
||||
def i64immZExt32 : PatLeaf<(i64 imm), [{
|
||||
// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
|
||||
// zero extended field.
|
||||
return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
|
||||
}]>;
|
||||
|
||||
// extloads
|
||||
def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
|
||||
def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
|
||||
def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
|
||||
def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
|
||||
def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
|
||||
|
||||
def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
|
||||
def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
|
||||
def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
|
||||
def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
|
||||
def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
|
||||
|
||||
def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
|
||||
def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
|
||||
def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
|
||||
def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
|
||||
def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
|
||||
|
||||
// A couple of more descriptive operand definitions.
|
||||
// 32-bits but only 8 bits are significant.
|
||||
def i32i8imm : Operand<i32>;
|
||||
// 32-bits but only 16 bits are significant.
|
||||
def i32i16imm : Operand<i32>;
|
||||
// 64-bits but only 32 bits are significant.
|
||||
def i64i32imm : Operand<i64>;
|
||||
// Branch targets have OtherVT type.
|
||||
def brtarget : Operand<OtherVT>;
|
||||
|
||||
// Unigned i12
|
||||
def u12imm : Operand<i32> {
|
||||
let PrintMethod = "printU16ImmOperand";
|
||||
}
|
||||
// Signed i16
|
||||
def s16imm : Operand<i32> {
|
||||
let PrintMethod = "printS16ImmOperand";
|
||||
}
|
||||
def s16imm64 : Operand<i64> {
|
||||
let PrintMethod = "printS16ImmOperand";
|
||||
}
|
||||
// Signed i20
|
||||
def s20imm : Operand<i32> {
|
||||
let PrintMethod = "printS20ImmOperand";
|
||||
}
|
||||
def s20imm64 : Operand<i64> {
|
||||
let PrintMethod = "printS20ImmOperand";
|
||||
}
|
||||
// Signed i32
|
||||
def s32imm : Operand<i32> {
|
||||
let PrintMethod = "printS32ImmOperand";
|
||||
}
|
||||
def s32imm64 : Operand<i64> {
|
||||
let PrintMethod = "printS32ImmOperand";
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SystemZ Operand Definitions.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Address operands
|
||||
|
||||
// riaddr := reg + imm
|
||||
def riaddr32 : Operand<i32>,
|
||||
ComplexPattern<i32, 2, "SelectAddrRI32", []> {
|
||||
let PrintMethod = "printRIAddrOperand";
|
||||
let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp);
|
||||
}
|
||||
|
||||
def riaddr : Operand<i64>,
|
||||
ComplexPattern<i64, 2, "SelectAddrRI", []> {
|
||||
let PrintMethod = "printRIAddrOperand";
|
||||
let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp);
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// rriaddr := reg + reg + imm
|
||||
def rriaddr : Operand<i64>,
|
||||
ComplexPattern<i64, 3, "SelectAddrRRI", [], []> {
|
||||
let PrintMethod = "printRRIAddrOperand";
|
||||
let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
|
||||
}
|
||||
def laaddr : Operand<i64>,
|
||||
ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> {
|
||||
let PrintMethod = "printRRIAddrOperand";
|
||||
let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
|
||||
}
|
||||
@ -1,8 +1,7 @@
|
||||
; XFAIL: *
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nill | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nilh | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nihl | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nihh | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep ngr | count 4
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llilh | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llihl | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llihh | count 1
|
||||
|
||||
define i64 @foo1(i64 %a, i64 %b) {
|
||||
entry:
|
||||
|
||||
@ -1,6 +1,4 @@
|
||||
; XFAIL: *
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nill | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nilh | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep ngr | count 6
|
||||
|
||||
define i32 @foo1(i32 %a, i32 %b) {
|
||||
entry:
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep ngr | count 4
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep ngr | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nihf | count 1
|
||||
|
||||
define i32 @foo(i32 %a, i32 %b) {
|
||||
entry:
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgr | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgr | count 2
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nihf | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
|
||||
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep ogr | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nihf | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
|
||||
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep xgr | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nihf | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
|
||||
|
||||
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 2
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nill | count 1
|
||||
|
||||
define i32 @gnu_dev_major(i64 %__dev) nounwind readnone {
|
||||
entry:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user