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[Hexagon] Add aliases for vector loads/stores with no explicit offset
The mem(r0) instructions are treated as mem(r0+#0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268661 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
eb80fa1253
commit
8cb434aecf
@ -541,3 +541,82 @@ def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)",
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def : InstAlias<"$Rd.w = vextract($Vu, $Rs)",
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(V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>,
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Requires<[HasV60T]>;
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// Mapping from vtrans2x2(Vy32,Vx32,Rt32) to vshuff(Vy32,Vx32,Rt32)
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def : InstAlias<"vtrans2x2($Vy, $Vx, $Rt)",
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(V6_vshuff VectorRegs:$Vy, VectorRegs:$Vx, IntRegs:$Rt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"$Vt=vmem($Rs)",
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(V6_vL32b_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
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Requires<[HasV60T]>;
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def : InstAlias<"$Vt=vmem($Rs):nt",
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(V6_vL32b_nt_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
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Requires<[HasV60T]>;
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def : InstAlias<"vmem($Rs)=$Vt",
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(V6_vS32b_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"vmem($Rs):nt=$Vt",
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(V6_vS32b_nt_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"vmem($Rs)=$Vt.new",
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(V6_vS32b_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"vmem($Rs):nt=$Vt.new",
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(V6_vS32b_nt_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"if ($Qv) vmem($Rs)=$Vt",
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(V6_vS32b_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"if (!$Qv) vmem($Rs)=$Vt",
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(V6_vS32b_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"if ($Qv) vmem($Rs):nt=$Vt",
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(V6_vS32b_nt_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"if (!$Qv) vmem($Rs):nt=$Vt",
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(V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"if ($Pv) vmem($Rs)=$Vt",
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(V6_vS32b_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"if (!$Pv) vmem($Rs)=$Vt",
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(V6_vS32b_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"if ($Pv) vmem($Rs):nt=$Vt",
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(V6_vS32b_nt_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"if (!$Pv) vmem($Rs):nt=$Vt",
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(V6_vS32b_nt_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"$Vt=vmemu($Rs)",
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(V6_vL32Ub_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
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Requires<[HasV60T]>;
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def : InstAlias<"vmemu($Rs)=$Vt",
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(V6_vS32Ub_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"if ($Pv) vmemu($Rs)=$Vt",
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(V6_vS32Ub_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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def : InstAlias<"if (!$Pv) vmemu($Rs)=$Vt",
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(V6_vS32Ub_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
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Requires<[HasV60T]>;
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@ -44,3 +44,64 @@ q2 |= vcmp.eq(v11.uw, v12.uw)
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# CHECK: 1c8eed8b { q3 ^= vcmp.eq(v13.w,v14.w) }
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q3 ^= vcmp.eq(v13.uw, v14.uw)
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# CHECK: 2800c00f { v15 = vmem(r0+#0) }
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v15 = vmem(r0)
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# CHECK: 2841c010 { v16 = vmem(r1+#0):nt }
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v16 = vmem(r1):nt
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# CHECK: 2822c011 { vmem(r2+#0) = v17 }
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vmem(r2) = v17
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# CHECK: 2863c012 { vmem(r3+#0):nt = v18 }
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vmem(r3):nt = v18
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# CHECK: 2884c013 { if (q0) vmem(r4+#0) = v19 }
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if (q0) vmem(r4) = v19
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# CHECK: 2885c834 { if (!q1) vmem(r5+#0) = v20 }
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if (!q1) vmem(r5) = v20
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# CHECK: 28c6d015 { if (q2) vmem(r6+#0):nt = v21 }
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if (q2) vmem(r6):nt = v21
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# CHECK: 28c7d836 { if (!q3) vmem(r7+#0):nt = v22 }
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if (!q3) vmem(r7):nt = v22
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# CHECK: 28a8c017 { if (p0) vmem(r8+#0) = v23 }
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if (p0) vmem(r8) = v23
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# CHECK: 28a9c838 { if (!p1) vmem(r9+#0) = v24 }
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if (!p1) vmem(r9) = v24
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# CHECK: 28ead019 { if (p2) vmem(r10+#0):nt = v25 }
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if (p2) vmem(r10):nt = v25
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# CHECK: 28ebd83a { if (!p3) vmem(r11+#0):nt = v26 }
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if (!p3) vmem(r11):nt = v26
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# CHECK: 282cc022 vmem(r12+#0) = v27.new
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{
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v27 = vxor(v28, v29)
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vmem(r12) = v27.new
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}
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# CHECK: 286dc022 vmem(r13+#0):nt = v30.new
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{
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v30 = vxor(v31, v0)
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vmem(r13):nt = v30.new
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}
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# CHECK: 280ec0e1 { v1 = vmemu(r14+#0) }
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v1 = vmemu(r14)
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# CHECK: 282fc0e2 { vmemu(r15+#0) = v2 }
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vmemu(r15) = v2
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# CHECK: 28b0c0c3 { if (p0) vmemu(r16+#0) = v3 }
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if (p0) vmemu(r16) = v3
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# CHECK: 28b1c8e4 { if (!p1) vmemu(r17+#0) = v4 }
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if (!p1) vmemu(r17) = v4
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