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[SLP] Fixed non-deterministic behavior in Loop Vectorizer.
Differential Revision: https://reviews.llvm.org/D30638 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297257 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -93,7 +93,7 @@ struct VectorizerParams {
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class MemoryDepChecker {
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class MemoryDepChecker {
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public:
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public:
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typedef PointerIntPair<Value *, 1, bool> MemAccessInfo;
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typedef PointerIntPair<Value *, 1, bool> MemAccessInfo;
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typedef SmallPtrSet<MemAccessInfo, 8> MemAccessInfoSet;
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typedef SmallVector<MemAccessInfo, 8> MemAccessInfoList;
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/// \brief Set of potential dependent memory accesses.
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/// \brief Set of potential dependent memory accesses.
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typedef EquivalenceClasses<MemAccessInfo> DepCandidates;
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typedef EquivalenceClasses<MemAccessInfo> DepCandidates;
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@ -188,7 +188,7 @@ public:
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/// \brief Check whether the dependencies between the accesses are safe.
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/// \brief Check whether the dependencies between the accesses are safe.
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///
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///
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/// Only checks sets with elements in \p CheckDeps.
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/// Only checks sets with elements in \p CheckDeps.
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bool areDepsSafe(DepCandidates &AccessSets, MemAccessInfoSet &CheckDeps,
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bool areDepsSafe(DepCandidates &AccessSets, MemAccessInfoList &CheckDeps,
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const ValueToValueMap &Strides);
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const ValueToValueMap &Strides);
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/// \brief No memory dependence was encountered that would inhibit
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/// \brief No memory dependence was encountered that would inhibit
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@ -498,7 +498,7 @@ class AccessAnalysis {
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public:
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public:
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/// \brief Read or write access location.
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/// \brief Read or write access location.
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typedef PointerIntPair<Value *, 1, bool> MemAccessInfo;
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typedef PointerIntPair<Value *, 1, bool> MemAccessInfo;
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typedef SmallPtrSet<MemAccessInfo, 8> MemAccessInfoSet;
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typedef SmallVector<MemAccessInfo, 8> MemAccessInfoList;
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AccessAnalysis(const DataLayout &Dl, AliasAnalysis *AA, LoopInfo *LI,
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AccessAnalysis(const DataLayout &Dl, AliasAnalysis *AA, LoopInfo *LI,
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MemoryDepChecker::DepCandidates &DA,
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MemoryDepChecker::DepCandidates &DA,
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@ -550,7 +550,7 @@ public:
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DepChecker.clearDependences();
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DepChecker.clearDependences();
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}
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}
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MemAccessInfoSet &getDependenciesToCheck() { return CheckDeps; }
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MemAccessInfoList &getDependenciesToCheck() { return CheckDeps; }
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private:
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private:
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typedef SetVector<MemAccessInfo> PtrAccessSet;
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typedef SetVector<MemAccessInfo> PtrAccessSet;
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@ -564,8 +564,8 @@ private:
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const DataLayout &DL;
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const DataLayout &DL;
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/// Set of accesses that need a further dependence check.
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/// List of accesses that need a further dependence check.
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MemAccessInfoSet CheckDeps;
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MemAccessInfoList CheckDeps;
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/// Set of pointers that are read only.
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/// Set of pointers that are read only.
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SmallPtrSet<Value*, 16> ReadOnlyPtr;
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SmallPtrSet<Value*, 16> ReadOnlyPtr;
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@ -822,7 +822,7 @@ void AccessAnalysis::processMemAccesses() {
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// there is no other write to the ptr - this is an optimization to
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// there is no other write to the ptr - this is an optimization to
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// catch "a[i] = a[i] + " without having to do a dependence check).
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// catch "a[i] = a[i] + " without having to do a dependence check).
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if ((IsWrite || IsReadOnlyPtr) && SetHasWrite) {
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if ((IsWrite || IsReadOnlyPtr) && SetHasWrite) {
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CheckDeps.insert(Access);
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CheckDeps.push_back(Access);
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IsRTCheckAnalysisNeeded = true;
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IsRTCheckAnalysisNeeded = true;
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}
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}
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@ -1530,12 +1530,14 @@ MemoryDepChecker::isDependent(const MemAccessInfo &A, unsigned AIdx,
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}
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}
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bool MemoryDepChecker::areDepsSafe(DepCandidates &AccessSets,
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bool MemoryDepChecker::areDepsSafe(DepCandidates &AccessSets,
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MemAccessInfoSet &CheckDeps,
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MemAccessInfoList &CheckDeps,
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const ValueToValueMap &Strides) {
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const ValueToValueMap &Strides) {
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MaxSafeDepDistBytes = -1;
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MaxSafeDepDistBytes = -1;
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while (!CheckDeps.empty()) {
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SmallPtrSet<MemAccessInfo, 8> Visited;
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MemAccessInfo CurAccess = *CheckDeps.begin();
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for (MemAccessInfo CurAccess : CheckDeps) {
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if (Visited.count(CurAccess))
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continue;
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// Get the relevant memory access set.
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// Get the relevant memory access set.
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EquivalenceClasses<MemAccessInfo>::iterator I =
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EquivalenceClasses<MemAccessInfo>::iterator I =
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@ -1549,7 +1551,7 @@ bool MemoryDepChecker::areDepsSafe(DepCandidates &AccessSets,
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// Check every access pair.
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// Check every access pair.
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while (AI != AE) {
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while (AI != AE) {
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CheckDeps.erase(*AI);
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Visited.insert(*AI);
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EquivalenceClasses<MemAccessInfo>::member_iterator OI = std::next(AI);
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EquivalenceClasses<MemAccessInfo>::member_iterator OI = std::next(AI);
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while (OI != AE) {
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while (OI != AE) {
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// Check every accessing instruction pair in program order.
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// Check every accessing instruction pair in program order.
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