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Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
opcode and operand with a tab. Check for these instructions in the usual places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -249,7 +249,8 @@ ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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// ...likewise if it ends with a branch table followed by an unconditional
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// ...likewise if it ends with a branch table followed by an unconditional
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// branch. The branch folder can create these, and we must get rid of them for
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// branch. The branch folder can create these, and we must get rid of them for
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// correctness of Thumb constant islands.
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// correctness of Thumb constant islands.
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if (isJumpTableBranchOpcode(SecondLastOpc) &&
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if ((isJumpTableBranchOpcode(SecondLastOpc) ||
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isIndirectBranchOpcode(SecondLastOpc)) &&
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isUncondBranchOpcode(LastOpc)) {
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isUncondBranchOpcode(LastOpc)) {
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I = LastInst;
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I = LastInst;
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if (AllowModify)
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if (AllowModify)
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@ -293,6 +293,11 @@ bool isJumpTableBranchOpcode(int Opc) {
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Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
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Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
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}
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}
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static inline
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bool isIndirectBranchOpcode(int Opc) {
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return Opc == ARM::BRIND || Opc == ARM::tBRIND;
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}
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/// getInstrPredicate - If instruction is predicated, returns its predicate
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/// getInstrPredicate - If instruction is predicated, returns its predicate
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/// condition, otherwise returns AL. It also returns the condition code
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/// condition, otherwise returns AL. It also returns the condition code
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/// register by reference.
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/// register by reference.
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@ -67,6 +67,7 @@ bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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case ARM::BX_RET: // Return.
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case ARM::BX_RET: // Return.
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case ARM::LDM_RET:
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case ARM::LDM_RET:
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case ARM::B:
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case ARM::B:
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case ARM::BRIND:
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case ARM::BR_JTr: // Jumptable branch.
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case ARM::BR_JTr: // Jumptable branch.
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case ARM::BR_JTm: // Jumptable branch through mem.
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case ARM::BR_JTm: // Jumptable branch through mem.
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case ARM::BR_JTadd: // Jumptable branch add to pc.
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case ARM::BR_JTadd: // Jumptable branch add to pc.
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@ -659,7 +659,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in
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// Indirect branches
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// Indirect branches
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx $dst",
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def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
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[(brind GPR:$dst)]> {
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[(brind GPR:$dst)]> {
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let Inst{7-4} = 0b0001;
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let Inst{7-4} = 0b0001;
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let Inst{19-8} = 0b111111111111;
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let Inst{19-8} = 0b111111111111;
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@ -180,6 +180,12 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>;
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def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>;
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}
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}
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// Indirect branches
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "bx\t$dst",
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[(brind GPR:$dst)]>;
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}
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// FIXME: remove when we have a way to marking a MI with these properties.
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// FIXME: remove when we have a way to marking a MI with these properties.
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
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hasExtraDefRegAllocReq = 1 in
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hasExtraDefRegAllocReq = 1 in
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@ -38,6 +38,7 @@ Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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case ARM::tBX_RET_vararg:
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case ARM::tBX_RET_vararg:
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case ARM::tPOP_RET:
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case ARM::tPOP_RET:
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case ARM::tB:
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case ARM::tB:
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case ARM::tBRIND:
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case ARM::tBR_JTr:
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case ARM::tBR_JTr:
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return true;
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return true;
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default:
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default:
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@ -46,6 +46,7 @@ Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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case ARM::tBX_RET_vararg:
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case ARM::tBX_RET_vararg:
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case ARM::tPOP_RET:
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case ARM::tPOP_RET:
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case ARM::tB:
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case ARM::tB:
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case ARM::tBRIND:
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return true;
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return true;
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default:
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default:
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break;
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break;
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