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Fix DwarfExpression::AddMachineRegExpression so it doesn't read past the

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end of an expression that ends with DW_OP_plus.
Caught by the ASAN build bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231260 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adrian Prantl 2015-03-04 17:39:33 +00:00
parent 506d4b2cb4
commit 8dd4cf1581
3 changed files with 18 additions and 14 deletions
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2
include/llvm/IR/DebugInfo.h
View File

@ -1031,7 +1031,7 @@ public:
/// \brief Returns underlying MDExpression::element_iterator.
const MDExpression::element_iterator &getBase() const { return I; }
/// \brief Returns the next operand.
Operand getNext() const;
iterator getNext() const;
};
/// \brief An iterator for DIExpression elements.

26
lib/CodeGen/AsmPrinter/DwarfExpression.cpp
View File

@ -196,11 +196,12 @@ bool DwarfExpression::AddMachineRegExpression(DIExpression Expr,
unsigned MachineReg,
unsigned PieceOffsetInBits) {
auto I = Expr.begin();
// Pattern-match combinations for which more efficient representations exist
// first.
if (I == Expr.end())
auto E = Expr.end();
if (I == E)
return AddMachineRegPiece(MachineReg);
// Pattern-match combinations for which more efficient representations exist
// first.
bool ValidReg = false;
switch (*I) {
case dwarf::DW_OP_bit_piece: {
@ -210,20 +211,23 @@ bool DwarfExpression::AddMachineRegExpression(DIExpression Expr,
return AddMachineRegPiece(MachineReg, SizeInBits,
getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
}
case dwarf::DW_OP_plus:
case dwarf::DW_OP_plus: {
// [DW_OP_reg,Offset,DW_OP_plus,DW_OP_deref] --> [DW_OP_breg,Offset].
if (I->getNext() == dwarf::DW_OP_deref) {
auto N = I->getNext();
if ((N != E) && (*N == dwarf::DW_OP_deref)) {
unsigned Offset = I->getArg(1);
ValidReg = AddMachineRegIndirect(MachineReg, Offset);
std::advance(I, 2);
break;
} else
ValidReg = AddMachineRegPiece(MachineReg);
case dwarf::DW_OP_deref:
// [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
ValidReg = AddMachineRegIndirect(MachineReg);
++I;
break;
}
case dwarf::DW_OP_deref: {
// [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
ValidReg = AddMachineRegIndirect(MachineReg);
++I;
break;
}
default:
llvm_unreachable("unsupported operand");
}
@ -232,7 +236,7 @@ bool DwarfExpression::AddMachineRegExpression(DIExpression Expr,
return false;
// Emit remaining elements of the expression.
AddExpression(I, Expr.end(), PieceOffsetInBits);
AddExpression(I, E, PieceOffsetInBits);
return true;
}

4
lib/IR/DebugInfo.cpp
View File

@ -183,9 +183,9 @@ uint64_t DIExpression::getBitPieceSize() const {
return getElement(getNumElements()-1);
}
DIExpression::Operand DIExpression::Operand::getNext() const {
DIExpression::iterator DIExpression::Operand::getNext() const {
iterator it(I);
return *(++it);
return ++it;
}
//===----------------------------------------------------------------------===//