R600: Emit CF_ALU and use true kcache register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178503 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune 2013-04-01 21:47:42 +00:00
parent 19801a6481
commit 8e59191eb8
7 changed files with 398 additions and 11 deletions

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@ -23,6 +23,7 @@ class AMDGPUTargetMachine;
// R600 Passes
FunctionPass* createR600KernelParametersPass(const DataLayout *TD);
FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
FunctionPass *createR600EmitClauseMarkers(TargetMachine &tm);
// SI Passes
FunctionPass *createSIAnnotateControlFlowPass();

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@ -151,6 +151,7 @@ bool AMDGPUPassConfig::addPreEmitPass() {
if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
addPass(createAMDGPUCFGPreparationPass(*TM));
addPass(createAMDGPUCFGStructurizerPass(*TM));
addPass(createR600EmitClauseMarkers(*TM));
addPass(createR600ExpandSpecialInstrsPass(*TM));
addPass(&FinalizeMachineBundlesID);
} else {

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@ -101,7 +101,8 @@ enum InstrTypes {
INSTR_FC,
INSTR_NATIVE,
INSTR_VTX,
INSTR_EXPORT
INSTR_EXPORT,
INSTR_CFALU
};
enum FCInstr {
@ -251,6 +252,13 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
Emit(Inst, OS);
break;
}
case AMDGPU::CF_ALU:
case AMDGPU::CF_ALU_PUSH_BEFORE: {
uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
EmitByte(INSTR_CFALU, OS);
Emit(Inst, OS);
break;
}
default:
EmitALUInstr(MI, Fixups, OS);

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@ -0,0 +1,253 @@
//===-- R600EmitClauseMarkers.cpp - Emit CF_ALU ---------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// Add CF_ALU. R600 Alu instructions are grouped in clause which can hold
/// 128 Alu instructions ; these instructions can access up to 4 prefetched
/// 4 lines of 16 registers from constant buffers. Such ALU clauses are
/// initiated by CF_ALU instructions.
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "R600Defines.h"
#include "R600InstrInfo.h"
#include "R600MachineFunctionInfo.h"
#include "R600RegisterInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
namespace llvm {
class R600EmitClauseMarkersPass : public MachineFunctionPass {
private:
static char ID;
const R600InstrInfo *TII;
unsigned OccupiedDwords(MachineInstr *MI) const {
switch (MI->getOpcode()) {
case AMDGPU::INTERP_PAIR_XY:
case AMDGPU::INTERP_PAIR_ZW:
case AMDGPU::INTERP_VEC_LOAD:
case AMDGPU::DOT4_eg_pseudo:
case AMDGPU::DOT4_r600_pseudo:
return 4;
case AMDGPU::KILL:
return 0;
default:
break;
}
if(TII->isVector(*MI) ||
TII->isCubeOp(MI->getOpcode()) ||
TII->isReductionOp(MI->getOpcode()))
return 4;
unsigned NumLiteral = 0;
for (MachineInstr::mop_iterator It = MI->operands_begin(),
E = MI->operands_end(); It != E; ++It) {
MachineOperand &MO = *It;
if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
++NumLiteral;
}
return 1 + NumLiteral;
}
bool isALU(const MachineInstr *MI) const {
if (MI->getOpcode() == AMDGPU::KILLGT)
return false;
if (TII->isALUInstr(MI->getOpcode()))
return true;
if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode()))
return true;
switch (MI->getOpcode()) {
case AMDGPU::PRED_X:
case AMDGPU::INTERP_PAIR_XY:
case AMDGPU::INTERP_PAIR_ZW:
case AMDGPU::INTERP_VEC_LOAD:
case AMDGPU::COPY:
case AMDGPU::DOT4_eg_pseudo:
case AMDGPU::DOT4_r600_pseudo:
return true;
default:
return false;
}
}
bool IsTrivialInst(MachineInstr *MI) const {
switch (MI->getOpcode()) {
case AMDGPU::KILL:
case AMDGPU::RETURN:
return true;
default:
return false;
}
}
// Register Idx, then Const value
std::vector<std::pair<unsigned, unsigned> > ExtractConstRead(MachineInstr *MI)
const {
const R600Operands::Ops OpTable[3][2] = {
{R600Operands::SRC0, R600Operands::SRC0_SEL},
{R600Operands::SRC1, R600Operands::SRC1_SEL},
{R600Operands::SRC2, R600Operands::SRC2_SEL},
};
std::vector<std::pair<unsigned, unsigned> > Result;
if (!TII->isALUInstr(MI->getOpcode()))
return Result;
for (unsigned j = 0; j < 3; j++) {
int SrcIdx = TII->getOperandIdx(MI->getOpcode(), OpTable[j][0]);
if (SrcIdx < 0)
break;
if (MI->getOperand(SrcIdx).getReg() == AMDGPU::ALU_CONST) {
unsigned Const = MI->getOperand(
TII->getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
Result.push_back(std::pair<unsigned, unsigned>(SrcIdx, Const));
}
}
return Result;
}
std::pair<unsigned, unsigned> getAccessedBankLine(unsigned Sel) const {
// Sel is (512 + (kc_bank << 12) + ConstIndex) << 2
// (See also R600ISelLowering.cpp)
// ConstIndex value is in [0, 4095];
return std::pair<unsigned, unsigned>(
((Sel >> 2) - 512) >> 12, // KC_BANK
// Line Number of ConstIndex
// A line contains 16 constant registers however KCX bank can lock
// two line at the same time ; thus we want to get an even line number.
// Line number can be retrieved with (>>4), using (>>5) <<1 generates
// an even number.
((((Sel >> 2) - 512) & 4095) >> 5) << 1);
}
bool SubstituteKCacheBank(MachineInstr *MI,
std::vector<std::pair<unsigned, unsigned> > &CachedConsts) const {
std::vector<std::pair<unsigned, unsigned> > UsedKCache;
std::vector<std::pair<unsigned, unsigned> > Consts = ExtractConstRead(MI);
assert(TII->isALUInstr(MI->getOpcode()) && "Can't assign Const");
for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
unsigned Sel = Consts[i].second;
unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
unsigned KCacheIndex = Index * 4 + Chan;
const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
if (CachedConsts.empty()) {
CachedConsts.push_back(BankLine);
UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
continue;
}
if (CachedConsts[0] == BankLine) {
UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
continue;
}
if (CachedConsts.size() == 1) {
CachedConsts.push_back(BankLine);
UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
continue;
}
if (CachedConsts[1] == BankLine) {
UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
continue;
}
return false;
}
for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
switch(UsedKCache[i].first) {
case 0:
MI->getOperand(Consts[i].first).setReg(
AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[i].second));
break;
case 1:
MI->getOperand(Consts[i].first).setReg(
AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[i].second));
break;
default:
llvm_unreachable("Wrong Cache Line");
}
}
return true;
}
MachineBasicBlock::iterator
MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const {
MachineBasicBlock::iterator ClauseHead = I;
std::vector<std::pair<unsigned, unsigned> > KCacheBanks;
bool PushBeforeModifier = false;
unsigned AluInstCount = 0;
for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
if (IsTrivialInst(I))
continue;
if (!isALU(I))
break;
if (I->getOpcode() == AMDGPU::PRED_X) {
if (TII->getFlagOp(I).getImm() & MO_FLAG_PUSH)
PushBeforeModifier = true;
AluInstCount ++;
continue;
}
if (TII->isALUInstr(I->getOpcode()) &&
!SubstituteKCacheBank(I, KCacheBanks))
break;
AluInstCount += OccupiedDwords(I);
if (AluInstCount > 124)
break;
}
unsigned Opcode = PushBeforeModifier ?
AMDGPU::CF_ALU_PUSH_BEFORE : AMDGPU::CF_ALU;
BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
.addImm(0) // ADDR
.addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0
.addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1
.addImm(KCacheBanks.empty()?0:2) // KM0
.addImm((KCacheBanks.size() < 2)?0:2) // KM1
.addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0
.addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1
.addImm(AluInstCount); // COUNT
return I;
}
public:
R600EmitClauseMarkersPass(TargetMachine &tm) : MachineFunctionPass(ID),
TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
virtual bool runOnMachineFunction(MachineFunction &MF) {
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
MachineBasicBlock::iterator I = MBB.begin();
if (I->getOpcode() == AMDGPU::CF_ALU)
continue; // BB was already parsed
for (MachineBasicBlock::iterator E = MBB.end(); I != E;) {
if (isALU(I))
I = MakeALUClause(MBB, I);
else
++I;
}
}
return false;
}
const char *getPassName() const {
return "R600 Emit Clause Markers Pass";
}
};
char R600EmitClauseMarkersPass::ID = 0;
}
llvm::FunctionPass *llvm::createR600EmitClauseMarkers(TargetMachine &TM) {
return new R600EmitClauseMarkersPass(TM);
}

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@ -351,9 +351,9 @@ class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
(ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
!strconcat(opName,
!strconcat(" ", opName,
"$clamp $dst$write$dst_rel$omod, "
"$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
"$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
"$literal $pred_sel$last"),
pattern,
itin>,
@ -392,10 +392,10 @@ class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
!strconcat(opName,
!strconcat(" ", opName,
"$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
"$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
"$src1_neg$src1_abs$src1$src1_sel$src1_abs$src1_rel, "
"$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
"$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
"$literal $pred_sel$last"),
pattern,
itin>,
@ -430,10 +430,10 @@ class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
!strconcat(opName, "$clamp $dst$dst_rel, "
"$src0_neg$src0$src0_sel$src0_rel, "
"$src1_neg$src1$src1_sel$src1_rel, "
"$src2_neg$src2$src2_sel$src2_rel, "
!strconcat(" ", opName, "$clamp $dst$dst_rel, "
"$src0_neg$src0$src0_rel, "
"$src1_neg$src1$src1_rel, "
"$src2_neg$src2$src2_rel, "
"$literal $pred_sel$last"),
pattern,
itin>,
@ -765,6 +765,67 @@ class ExportBufInst : InstR600ISA<(
let Inst{63-32} = Word1;
}
//===----------------------------------------------------------------------===//
// Control Flow Instructions
//===----------------------------------------------------------------------===//
class CF_ALU_WORD0 {
field bits<32> Word0;
bits<22> ADDR;
bits<4> KCACHE_BANK0;
bits<4> KCACHE_BANK1;
bits<2> KCACHE_MODE0;
let Word0{21-0} = ADDR;
let Word0{25-22} = KCACHE_BANK0;
let Word0{29-26} = KCACHE_BANK1;
let Word0{31-30} = KCACHE_MODE0;
}
class CF_ALU_WORD1 {
field bits<32> Word1;
bits<2> KCACHE_MODE1;
bits<8> KCACHE_ADDR0;
bits<8> KCACHE_ADDR1;
bits<7> COUNT;
bits<1> ALT_CONST;
bits<4> CF_INST;
bits<1> WHOLE_QUAD_MODE;
bits<1> BARRIER;
let Word1{1-0} = KCACHE_MODE1;
let Word1{9-2} = KCACHE_ADDR0;
let Word1{17-10} = KCACHE_ADDR1;
let Word1{24-18} = COUNT;
let Word1{25} = ALT_CONST;
let Word1{29-26} = CF_INST;
let Word1{30} = WHOLE_QUAD_MODE;
let Word1{31} = BARRIER;
}
class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
(ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, i32imm:$KCACHE_MODE0, i32imm:$KCACHE_MODE1,
i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, i32imm:$COUNT),
!strconcat(OpName, " $COUNT, @$ADDR, "
"KC0[CB$KCACHE_BANK0:$KCACHE_ADDR0-$KCACHE_ADDR0+32]"
", KC1[CB$KCACHE_BANK1:$KCACHE_ADDR1-$KCACHE_ADDR1+32]"),
[] >, CF_ALU_WORD0, CF_ALU_WORD1 {
field bits<64> Inst;
let CF_INST = inst;
let ALT_CONST = 0;
let WHOLE_QUAD_MODE = 0;
let BARRIER = 1;
let Inst{31-0} = Word0;
let Inst{63-32} = Word1;
}
def CF_ALU : ALU_CLAUSE<8, "ALU">;
def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
let Predicates = [isR600toCayman] in {
//===----------------------------------------------------------------------===//

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@ -43,6 +43,37 @@ foreach Index = 0-127 in {
Index>;
}
// KCACHE_BANK0
foreach Index = 159-128 in {
foreach Chan = [ "X", "Y", "Z", "W" ] in {
// 32-bit Temporary Registers
def KC0_#Index#_#Chan : R600RegWithChan <"KC0["#Index#"-128]."#Chan, Index, Chan>;
}
// 128-bit Temporary Registers
def KC0_#Index#_XYZW : R600Reg_128 <"KC0["#Index#"-128].XYZW",
[!cast<Register>("KC0_"#Index#"_X"),
!cast<Register>("KC0_"#Index#"_Y"),
!cast<Register>("KC0_"#Index#"_Z"),
!cast<Register>("KC0_"#Index#"_W")],
Index>;
}
// KCACHE_BANK1
foreach Index = 191-160 in {
foreach Chan = [ "X", "Y", "Z", "W" ] in {
// 32-bit Temporary Registers
def KC1_#Index#_#Chan : R600RegWithChan <"KC1["#Index#"-160]."#Chan, Index, Chan>;
}
// 128-bit Temporary Registers
def KC1_#Index#_XYZW : R600Reg_128 <"KC1["#Index#"-160].XYZW",
[!cast<Register>("KC1_"#Index#"_X"),
!cast<Register>("KC1_"#Index#"_Y"),
!cast<Register>("KC1_"#Index#"_Z"),
!cast<Register>("KC1_"#Index#"_W")],
Index>;
}
// Array Base Register holding input in FS
foreach Index = 448-480 in {
def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>;
@ -80,6 +111,38 @@ def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X",
} // End isAllocatable = 0
def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "KC0_%u_X", 128, 159))>;
def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "KC0_%u_Y", 128, 159))>;
def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "KC0_%u_Z", 128, 159))>;
def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "KC0_%u_W", 128, 159))>;
def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
(interleave R600_KC0_X, R600_KC0_Y,
R600_KC0_Z, R600_KC0_W)>;
def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "KC1_%u_X", 160, 191))>;
def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "KC1_%u_Y", 160, 191))>;
def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "KC1_%u_Z", 160, 191))>;
def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "KC1_%u_W", 160, 191))>;
def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32,
(interleave R600_KC1_X, R600_KC1_Y,
R600_KC1_Z, R600_KC1_W)>;
def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "T%u_X", 0, 127), AR_X)>;

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@ -1,7 +1,7 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK: @main1
; CHECK: MOV T{{[0-9]+\.[XYZW], CBuf0\[[0-9]+\]\.[XYZW]}}
; CHECK: MOV T{{[0-9]+\.[XYZW], KC0}}
define void @main1() {
main_body:
%0 = load <4 x float> addrspace(8)* null