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[AVR] Add MIR tests for pseudo instruction expansions

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This adds tests for 13 pseudo instruction expansions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289039 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dylan McKay 2016-12-08 10:52:13 +00:00
parent bbc30ffcb6
commit 8f6ef5fefd
13 changed files with 308 additions and 0 deletions
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24
test/CodeGen/AVR/pseudo/ADCWRdRr.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit add with carry pseudo instruction.
--- |
target triple = "avr--"
define void @test_adcwrdrr() {
entry:
ret void
}
...
---
name: test_adcwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_adcwrdrr
; CHECK: %r14 = ADCRdRr %r14, %r20, implicit-def %sreg, implicit %sreg
; CHECK-LABEL: %r15 = ADCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
%r15r14 = ADCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
...

24
test/CodeGen/AVR/pseudo/ANDIWRdK.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit ANDO pseudo instruction.
--- |
target triple = "avr--"
define void @test_andiwrdrr() {
entry:
ret void
}
...
---
name: test_andiwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_andiwrdrr
; CHECK: %r20 = ANDIRdK %r20, 175, implicit-def dead %sreg
; CHECK-NEXT: %r21 = ANDIRdK %r21, 250, implicit-def %sreg
%r21r20 = ANDIWRdK %r17r16, 64175, implicit-def %sreg
...

24
test/CodeGen/AVR/pseudo/ANDWRdRr.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit AND pseudo instruction.
--- |
target triple = "avr--"
define void @test_andwrdrr() {
entry:
ret void
}
...
---
name: test_andwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_andwrdrr
; CHECK: %r14 = ANDRdRr %r14, %r20, implicit-def dead %sreg
; CHECK-NEXT: %r15 = ANDRdRr %r15, %r21, implicit-def %sreg
%r15r14 = ANDWRdRr %r15r14, %r21r20, implicit-def %sreg
...

24
test/CodeGen/AVR/pseudo/COMWRd.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit COM pseudo instruction.
--- |
target triple = "avr--"
define void @test_comwrd() {
entry:
ret void
}
...
---
name: test_comwrd
body: |
bb.0.entry:
; CHECK-LABEL: test_comwrd
; CHECK: %r14 = COMRd %r14, implicit-def dead %sreg
; CHECK-NEXT: %r15 = COMRd %r15, implicit-def %sreg
%r15r14 = COMWRd %r9r8, implicit-def %sreg
...

22
test/CodeGen/AVR/pseudo/CPCWRdRr.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# XFAIL: *
# This test checks the expansion of the 16-bit CPCW pseudo instruction.
--- |
target triple = "avr--"
define void @test_cpcwrdrr() {
entry:
ret void
}
...
---
name: test_cpcwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_cpcwrdrr
%r15r14 = CPCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
...

22
test/CodeGen/AVR/pseudo/CPWRdRr.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# XFAIL: *
# This test checks the expansion of the 16-bit CPW pseudo instruction.
--- |
target triple = "avr--"
define void @test_cpwrdrr() {
entry:
ret void
}
...
---
name: test_cpwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_cpwrdrr
%r15r14 = CPWRdRr %r15r14, %r21r20, implicit-def %sreg
...

24
test/CodeGen/AVR/pseudo/EORWRdRr.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit EOR pseudo instruction.
--- |
target triple = "avr--"
define void @test_eorwrdrr() {
entry:
ret void
}
...
---
name: test_eorwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_eorwrdrr
; CHECK: %r14 = EORRdRr %r14, %r20, implicit-def dead %sreg
; CHECK-NEXT: %r15 = EORRdRr %r15, %r21, implicit-def %sreg
%r15r14 = EORWRdRr %r15r14, %r21r20, implicit-def %sreg
...

24
test/CodeGen/AVR/pseudo/ORIWRdK.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit OR pseudo instruction.
--- |
target triple = "avr--"
define void @test_oriwrdrr() {
entry:
ret void
}
...
---
name: test_oriwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_oriwrdrr
; CHECK: %r20 = ORIRdK %r20, 175, implicit-def dead %sreg
; CHECK-NEXT: %r21 = ORIRdK %r21, 250, implicit-def %sreg
%r21r20 = ORIWRdK %r17r16, 64175, implicit-def %sreg
...

24
test/CodeGen/AVR/pseudo/ORWRdRr.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit OR pseudo instruction.
--- |
target triple = "avr--"
define void @test_orwrdrr() {
entry:
ret void
}
...
---
name: test_orwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_orwrdrr
; CHECK: %r14 = ORRdRr %r14, %r20, implicit-def dead %sreg
; CHECK-NEXT: %r15 = ORRdRr %r15, %r21, implicit-def %sreg
%r15r14 = ORWRdRr %r15r14, %r21r20, implicit-def %sreg
...

24
test/CodeGen/AVR/pseudo/SBCIWRdK.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit subtraction with carry pseudo instruction.
--- |
target triple = "avr--"
define void @test_sbciwrdk() {
entry:
ret void
}
...
---
name: test_sbciwrdk
body: |
bb.0.entry:
; CHECK-LABEL: test_sbciwrdk
; CHECK: %r20 = SBCIRdK %r20, 175, implicit-def %sreg, implicit killed %sreg
; CHECK-NEXT: %r21 = SBCIRdK %r21, 250, implicit-def %sreg, implicit killed %sreg
%r21r20 = SBCIWRdK %r17r16, 64175, implicit-def %sreg, implicit %sreg
...

24
test/CodeGen/AVR/pseudo/SBCWRdRr.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit subtraction with carry pseudo instruction.
--- |
target triple = "avr--"
define void @test_sbcwrdrr() {
entry:
ret void
}
...
---
name: test_sbcwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_sbcwrdrr
; CHECK: %r14 = SBCRdRr %r14, %r20, implicit-def %sreg
; CHECK-NEXT: %r15 = SBCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
%r15r14 = SBCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
...

24
test/CodeGen/AVR/pseudo/SUBIWRdK.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit subtraction pseudo instruction.
--- |
target triple = "avr--"
define void @test_subiwrdrr() {
entry:
ret void
}
...
---
name: test_subiwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_subiwrdrr
; CHECK: %r20 = SUBIRdK %r20, 175, implicit-def %sreg
; CHECK-NEXT: %r21 = SBCIRdK %r21, 250, implicit-def %sreg, implicit killed %sreg
%r21r20 = SUBIWRdK %r17r16, 64175, implicit-def %sreg
...

24
test/CodeGen/AVR/pseudo/SUBWRdRr.mir Normal file
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
# This test checks the expansion of the 16-bit subtraction pseudo instruction.
--- |
target triple = "avr--"
define void @test_subwrdrr() {
entry:
ret void
}
...
---
name: test_subwrdrr
body: |
bb.0.entry:
; CHECK-LABEL: test_subwrdrr
; CHECK: %r14 = SUBRdRr %r14, %r20, implicit-def %sreg
; CHECK-NEXT: %r15 = SBCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
%r15r14 = SUBWRdRr %r15r14, %r21r20, implicit-def %sreg
...