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[SimplifyCFG] Make range reduction code deterministic.

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This generated IR based on the order of evaluation, which is different
between GCC and Clang. With that in mind you get bootstrap miscompares
if you compare a Clang built with GCC-built Clang vs. Clang built with
Clang-built Clang. Diagnosing that made my head hurt.

This also reverts commit r277337, which "fixed" the test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277820 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2016-08-05 14:55:02 +00:00
parent 1c1a94675a
commit 904a5364dd
2 changed files with 23 additions and 22 deletions
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5
lib/Transforms/Utils/SimplifyCFG.cpp
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@ -5128,8 +5128,9 @@ static bool ReduceSwitchRange(SwitchInst *SI, IRBuilder<> &Builder,
Builder.SetInsertPoint(SI);
auto *ShiftC = ConstantInt::get(Ty, Shift);
auto *Sub = Builder.CreateSub(SI->getCondition(), ConstantInt::get(Ty, Base));
auto *Rot = Builder.CreateOr(Builder.CreateLShr(Sub, ShiftC),
Builder.CreateShl(Sub, Ty->getBitWidth() - Shift));
auto *LShr = Builder.CreateLShr(Sub, ShiftC);
auto *Shl = Builder.CreateShl(Sub, Ty->getBitWidth() - Shift);
auto *Rot = Builder.CreateOr(LShr, Shl);
SI->replaceUsesOfWith(SI->getCondition(), Rot);
for (SwitchInst::CaseIt C = SI->case_begin(), E = SI->case_end(); C != E;

40
test/Transforms/SimplifyCFG/rangereduce.ll
View File

@ -3,11 +3,11 @@
target datalayout = "e-n32"
; CHECK-LABEL: @test1
; CHECK: %[[SUB:.*]] = sub i32 %a, 97
; CHECK-DAG: %[[LSHR:.*]] = lshr i32 %[[SUB]], 2
; CHECK-DAG: %[[SHL:.*]] = shl i32 %[[SUB]], 30
; CHECK: %[[OR:.*]] = or i32 %[[LSHR]], %[[SHL]]
; CHECK: switch i32 %[[OR]], label %def [
; CHECK: %1 = sub i32 %a, 97
; CHECK-DAG: %2 = lshr i32 %1, 2
; CHECK-DAG: %3 = shl i32 %1, 30
; CHECK: %4 = or i32 %2, %3
; CHECK: switch i32 %4, label %def [
; CHECK: i32 0, label %one
; CHECK: i32 1, label %two
; CHECK: i32 2, label %three
@ -120,11 +120,11 @@ three:
}
; CHECK-LABEL: @test6
; CHECK: %[[SUB:.*]] = sub i32 %a, -109
; CHECK-DAG: %[[LSHR:.*]] = lshr i32 %[[SUB]], 2
; CHECK-DAG: %[[SHL:.*]] = shl i32 %[[SUB]], 30
; CHECK: %[[OR:.*]] = or i32 %[[LSHR]], %[[SHL]]
; CHECK: switch i32 %[[OR]], label %def [
; CHECK: %1 = sub i32 %a, -109
; CHECK-DAG: %2 = lshr i32 %1, 2
; CHECK-DAG: %3 = shl i32 %1, 30
; CHECK: %4 = or i32 %2, %3
; CHECK: switch i32 %4, label %def [
define i32 @test6(i32 %a) optsize {
switch i32 %a, label %def [
i32 -97, label %one
@ -145,11 +145,11 @@ three:
}
; CHECK-LABEL: @test7
; CHECK: %[[SUB:.*]] = sub i8 %a, -36
; CHECK-DAG: %[[LSHR:.*]] = lshr i8 %[[SUB]], 2
; CHECK-DAG: %[[SHL:.*]] = shl i8 %[[SUB]], 6
; CHECK: %[[OR:.*]] = or i8 %[[LSHR]], %[[SHL]]
; CHECK: switch.tableidx = {{.*}} %[[OR]]
; CHECK: %1 = sub i8 %a, -36
; CHECK-DAG: %2 = lshr i8 %1, 2
; CHECK-DAG: %3 = shl i8 %1, 6
; CHECK: %4 = or i8 %2, %3
; CHECK: switch.tableidx = {{.*}} %4
define i8 @test7(i8 %a) optsize {
switch i8 %a, label %def [
i8 220, label %one
@ -170,11 +170,11 @@ three:
}
; CHECK-LABEL: @test8
; CHECK: %[[SUB:.*]] = sub i32 %a, 97
; CHECK-DAG: %[[LSHR:.*]] = lshr i32 %1, 2
; CHECK-DAG: %[[SHL:.*]] = shl i32 %1, 30
; CHECK: %[[OR:.*]] = or i32 %[[LSHR]], %[[SHL]]
; CHECK: switch i32 %[[OR]], label %def [
; CHECK: %1 = sub i32 %a, 97
; CHECK-DAG: %2 = lshr i32 %1, 2
; CHECK-DAG: %3 = shl i32 %1, 30
; CHECK: %4 = or i32 %2, %3
; CHECK: switch i32 %4, label %def [
define i32 @test8(i32 %a) optsize {
switch i32 %a, label %def [
i32 97, label %one