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another checkpoint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102052 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
7b91eda0de
commit
914ce46040
@ -75,6 +75,7 @@ Almost dead code.
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<!-- Features that need text if they're finished for 2.7:
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combiner-aa?
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strong phi elim
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llvm.dbg.value: variable debug info for optimized code
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loop dependence analysis
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@ -378,6 +379,15 @@ minor improvements. Some of the major improvements and new features are listed
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in this section.
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</p>
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</div>
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<!--=========================================================================-->
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<div class="doc_subsection">
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<a name="orgchanges">LLVM Community Changes</a>
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</div>
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<div class="doc_text">
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<p>In addition to changes to the code, between LLVM 2.6 and 2.7, a number of
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organization changes have happened:
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</p>
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@ -387,7 +397,7 @@ organization changes have happened:
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<li>Ted Kremenek and Doug Gregor have stepped forward as <a
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href="http://llvm.org/docs/DeveloperPolicy.html#owners">Code Owners</a> of the
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Clang static analyzer and the Clang Frontend, respectively.</li>
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Clang static analyzer and the Clang frontend, respectively.</li>
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<li>LLVM now has an <a href="http://blog.llvm.org">official Blog</a> at
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<a href="http://blog.llvm.org">http://blog.llvm.org</a>. This is a great way
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@ -480,9 +490,16 @@ expose new optimization opportunities:</p>
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allows the optimizer to infer the sizes of memory objects in some cases.
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This intrinsic is used to implement the GCC <tt>__builtin_object_size</tt>
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extension.</li>
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<li>LLVM IR now supports marking load and store instructions with <a
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href="LangRef.html#i_load">"non-temporal" hints</a> (building on the new
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metadata feature). This hint encourages the code
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generator to generate non-temporal accesses when possible, which are useful
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for code that is carefully managing cache behavior. Currently, only the
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X86 backend provides target support for this feature.</li>
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<li>LLVM 2.7 has pre-alpha support for <a
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href="http://llvm.org/docs/LangRef.html#t_union">unions in LLVM IR</a>.
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Unfortuantely, this support is not really usable in 2.7, so if you're
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Unfortunately, this support is not really usable in 2.7, so if you're
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interested in pushing it forward, please help contribute to LLVM mainline.</li>
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</li>
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</ul>
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@ -542,8 +559,7 @@ href="http://blog.llvm.org/2009/12/introduction-to-load-elimination-in-gvn.html"
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pointer offset expressions to disambiguate pointers. It can catch a few
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cases that basicaa cannot, particularly in complex loop nests.</li>
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<li>As usual, there are countless minor optimization improvements and bug fixes,
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and the default pass ordering has been tweaked for improved optimization
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<li>The default pass ordering has been tweaked for improved optimization
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effectiveness.</li>
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</ul>
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@ -563,8 +579,7 @@ href="http://blog.llvm.org/2009/12/introduction-to-load-elimination-in-gvn.html"
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the new GDB 7.0 (and later) interfaces for registering debug info for
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dynamically generated code.</li>
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<li>The JIT now <a
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href="http://llvm.org/viewvc/llvm-project?view=rev&revision=85295">defaults
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<li>The JIT now <a href="http://llvm.org/PR5184">defaults
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to compiling eagerly</a> to avoid a race condition in the lazy JIT.
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Clients that still want the lazy JIT can switch it on by calling
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<tt>ExecutionEngine::DisableLazyCompilation(false)</tt>.</li>
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@ -590,21 +605,48 @@ infrastructure, which allows us to implement more aggressive algorithms and make
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it run faster:</p>
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<ul>
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<li>New instruction selector [blog post?].</li>
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<li>New LSR with "full strength reduction" mode. Description?</li>
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<li>Code generator MC'ized except for debug info and EH.</li>
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<li>New CodeGen Level CSE</li>
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<li>Combiner-AA improvements, why not on by default?</li>
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<li>Pre-regalloc tail duplication</li>
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<li>Codegen level OptimizeExtsPass pass, takes advantage of x86 subregs. </li>
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<li>Support for the GCC option -fno-schedule-insns</li>
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<li>Non-temporal load/store, only implemented on X86, see LangRef.html#i_load.</li>
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<li>MachineSSAUpdater.h</li>
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<li>X86 and XCore supports returning arbitrary return values, returning too many values is
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supported by returning through a hidden pointer.</li>
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<li>verbose-asm now produces information about spill slots and loop nests</li>
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<li>GHC Haskell ABI / calling conv support.</li>
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<li>Many improvements to debug info</li>
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<li>The 'llc -asm-verbose' option (which is now the default) has been enhanced
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to emit many useful comments to .s files indicating information about spill
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slots and loop nest structure. This should make it much easier to read and
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understand assembly files. This is wired up in llvm-gcc and clang to
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the <tt>-fverbose-asm</tt> option.</li>
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<li>New LSR with "full strength reduction" mode. FIXME: Description?</li>
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<li>A new codegen level Common Subexpression Elimination pass (MachineCSE)
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is available and enabled by default. It catches redundancies exposed by
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lowering.</li>
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<li>A new pre-register-allocation tail duplication pass is available and enabled
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by default, it can substantially improve branch prediction quality in some
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cases.</li>
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<li>A new sign and zero extension optimization pass (OptimizeExtsPass)
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is available and enabled by default. This pass can takes advantage
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architecture features like x86-64 implicit zero extension behavior and
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sub-registers.</li>
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<li>The code generator now supports a mode where it attempts to preserve the
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order of instructions in the input code. This is important for source that
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is hand scheduled and extremely sensitive to scheduling. It is compatible
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with the GCC <tt>-fno-schedule-insns</tt> option.</li>
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<li>The target-independent code generator now supports generating code with
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arbitrary numbers of result values. Returning more values than was
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previously supported is handled by returning through a hidden pointer. In
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2.7, only the X86 and XCore targets have adopted support for this
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though.</li>
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<li>The code generator now supports generating code that follows the
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<a href="LangRef.html#callingconv">Glasgow Haskell Compiler Calling
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Convention</a> and ABI.</li>
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<li>The "<a href="CodeGenerator.html#selectiondag_select">DAG instruction
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selection</a>" phase of the code generator has been largely rewritten for
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2.7. Previously, tblgen spit out tons of C++ code which was compiled and
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linked into the target to do the pattern matching, now it emits a much
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smaller table which is read by the target-independent code. The primary
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advantages of this approach is that the size and compile time of various
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targets is much improved. The X86 code generator shrunk by 1.5MB of code,
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for example.</li>
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<li>Almost the entire code generator has switched to emitting code through the
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MC interfaces instead of printing textually to the .s file. This led to a
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number of cleanups and speedups. In 2.7, debug an exception handling
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information does not go through MC yet.</li>
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</ul>
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</div>
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@ -760,7 +802,7 @@ document.</li>
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<li>The LLVM interpreter now defaults to <em>not</em> using <tt>libffi</tt> even
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if you have it installed. This makes it more likely that an LLVM built on one
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system will work when copied to a similar system. To use <tt>libffi</tt>,
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configure with <tt>--enable-libffi</tt></li>.
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configure with <tt>--enable-libffi</tt>.</li>
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<li>Debug information uses a completely different representation, an LLVM 2.6
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.bc file should work with LLVM 2.7, but debug info won't come forward.</li>
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@ -827,7 +869,7 @@ to <tt>llvm/System/DataTypes.h</tt>.</li>
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<li>Intel and AMD machines (IA32, X86-64, AMD64, EMT-64) running Red Hat
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Linux, Fedora Core, FreeBSD and AuroraUX (and probably other unix-like
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systems).</li>
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<li>PowerPC and X86-based Mac OS X systems, running 10.3 and above in 32-bit
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<li>PowerPC and X86-based Mac OS X systems, running 10.4 and above in 32-bit
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and 64-bit modes.</li>
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<li>Intel and AMD machines running on Win32 using MinGW libraries (native).</li>
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<li>Intel and AMD machines running on Win32 with the Cygwin libraries (limited
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@ -884,7 +926,7 @@ href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVMdev list</a>.</p>
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<ul>
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<li>The MSIL, Alpha, SPU, MIPS, PIC16, Blackfin, MSP430, SystemZ and MicroBlaze
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backends are experimental.</li>
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<li>The <tt>llc</tt> "<tt>-filetype=asm</tt>" (the default) is the only
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<li><tt>llc</tt> "<tt>-filetype=asm</tt>" (the default) is the only
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supported value for this option. The MachO writer is experimental, and
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works much better in mainline SVN.</li>
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</ul>
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@ -907,13 +949,10 @@ href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVMdev list</a>.</p>
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to generate code for systems that don't have SSE2.</li>
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<li>Win64 code generation wasn't widely tested. Everything should work, but we
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expect small issues to happen. Also, llvm-gcc cannot build the mingw64
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runtime currently due
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to <a href="http://llvm.org/PR2255">several</a>
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<a href="http://llvm.org/PR2257">bugs</a> and due to lack of support for
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the
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'u' inline assembly constraint and for X87 floating point inline assembly.</li>
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runtime currently due to lack of support for the 'u' inline assembly
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constraint and for X87 floating point inline assembly.</li>
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<li>The X86-64 backend does not yet support the LLVM IR instruction
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<tt>va_arg</tt>. Currently, the llvm-gcc and front-ends support variadic
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<tt>va_arg</tt>. Currently, front-ends support variadic
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argument constructs on X86-64 by lowering them manually.</li>
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</ul>
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@ -1025,9 +1064,6 @@ appropriate nops inserted to ensure restartability.</li>
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supported on some targets (these are used when you take the address of a
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nested function).</p>
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<p>If you run into GCC extensions which are not supported, please let us know.
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</p>
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</div>
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<!-- ======================================================================= -->
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