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[Hexagon] Explicitly reserve aliases of reserved registers

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292836 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2017-01-23 22:13:05 +00:00
parent fc4ec25a17
commit 924f39dc83
2 changed files with 22 additions and 13 deletions
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33
lib/Target/Hexagon/HexagonRegisterInfo.cpp
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@ -139,19 +139,26 @@ BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
Reserved.set(Hexagon::R29);
Reserved.set(Hexagon::R30);
Reserved.set(Hexagon::R31);
Reserved.set(Hexagon::PC);
Reserved.set(Hexagon::D14);
Reserved.set(Hexagon::D15);
Reserved.set(Hexagon::LC0);
Reserved.set(Hexagon::LC1);
Reserved.set(Hexagon::SA0);
Reserved.set(Hexagon::SA1);
Reserved.set(Hexagon::UGP);
Reserved.set(Hexagon::GP);
Reserved.set(Hexagon::CS0);
Reserved.set(Hexagon::CS1);
Reserved.set(Hexagon::CS);
Reserved.set(Hexagon::USR);
Reserved.set(Hexagon::SA0); // C0
Reserved.set(Hexagon::LC0); // C1
Reserved.set(Hexagon::SA1); // C2
Reserved.set(Hexagon::LC1); // C3
Reserved.set(Hexagon::USR); // C8
Reserved.set(Hexagon::PC); // C9
Reserved.set(Hexagon::UGP); // C10
Reserved.set(Hexagon::GP); // C11
Reserved.set(Hexagon::CS0); // C12
Reserved.set(Hexagon::CS1); // C13
// Out of the control registers, only C8 is explicitly defined in
// HexagonRegisterInfo.td. If others are defined, make sure to add
// them here as well.
Reserved.set(Hexagon::C8);
Reserved.set(Hexagon::USR_OVF);
for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x))
markSuperRegs(Reserved, x);
return Reserved;
}

2
lib/Target/Hexagon/HexagonRegisterInfo.td
View File

@ -146,6 +146,8 @@ let Namespace = "Hexagon" in {
def LC1 : Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>;
def P3_0 : Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>,
DwarfRegNum<[71]>;
// When defining more Cn registers, make sure to explicitly mark them
// as reserved in HexagonRegisterInfo.cpp.
def C5 : Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>; // future use
def C6 : Rc<6, "c6", [], [M0]>, DwarfRegNum<[73]>;
def C7 : Rc<7, "c7", [], [M1]>, DwarfRegNum<[74]>;