RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-27 13:40:30 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

AMDGPU: Whitespace fixes

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306265 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2017-06-26 03:01:36 +00:00
parent ec6175c524
commit 92c7507eee
4 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/AMDGPU/AMDGPU.td
View File

@ -480,14 +480,14 @@ class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
[FeatureSouthernIslands,
FeatureFastFMAF32,
FeatureFastFMAF32,
HalfRate64Ops,
FeatureLDSBankCount32]>;
def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
[FeatureSouthernIslands,
FeatureLDSBankCount32]>;
def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
[FeatureSeaIslands,
FeatureLDSBankCount32]>;

2
lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
View File

@ -69,7 +69,7 @@ public:
unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
unsigned getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;

4
lib/Target/AMDGPU/Processors.td
View File

@ -80,7 +80,7 @@ def : Proc<"cayman", R600_VLIW4_Itin,
// Southern Islands
//===----------------------------------------------------------------------===//
def : ProcessorModel<"gfx600", SIFullSpeedModel,
def : ProcessorModel<"gfx600", SIFullSpeedModel,
[FeatureISAVersion6_0_0]>;
def : ProcessorModel<"SI", SIFullSpeedModel,
@ -95,7 +95,7 @@ def : ProcessorModel<"gfx601", SIQuarterSpeedModel,
[FeatureISAVersion6_0_1]
>;
def : ProcessorModel<"pitcairn", SIQuarterSpeedModel,
def : ProcessorModel<"pitcairn", SIQuarterSpeedModel,
[FeatureISAVersion6_0_1]>;
def : ProcessorModel<"verde", SIQuarterSpeedModel,

2
lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -1234,7 +1234,7 @@ static void reservePrivateMemoryRegs(const TargetMachine &TM,
}
}
if (NeedSP){
if (NeedSP) {
unsigned ReservedStackPtrOffsetReg = TRI.reservedStackPtrOffsetReg(MF);
Info.setStackPtrOffsetReg(ReservedStackPtrOffsetReg);