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Remove an apparently useless routine: there should
be no need to split the result of a vector RET node, since they are always already legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53462 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -440,7 +440,6 @@ private:
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SDOperand SplitVecOp_BIT_CONVERT(SDNode *N);
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SDOperand SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
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SDOperand SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
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SDOperand SplitVecOp_RET(SDNode *N, unsigned OpNo);
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SDOperand SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
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SDOperand SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo);
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@ -547,7 +547,6 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
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assert(0 && "Do not know how to split this operator's operand!");
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abort();
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case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
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case ISD::RET: Res = SplitVecOp_RET(N, OpNo); break;
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case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
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@ -604,19 +603,6 @@ SDOperand DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
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return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
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}
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SDOperand DAGTypeLegalizer::SplitVecOp_RET(SDNode *N, unsigned OpNo) {
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assert(N->getNumOperands() == 3 &&"Can only handle ret of one vector so far");
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// FIXME: Returns of gcc generic vectors larger than a legal vector
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// type should be returned by reference!
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SDOperand Lo, Hi;
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GetSplitVector(N->getOperand(1), Lo, Hi);
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SDOperand Chain = N->getOperand(0); // The chain.
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SDOperand Sign = N->getOperand(2); // Signness
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return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Sign, Hi, Sign);
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}
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SDOperand DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
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// For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
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// end up being split all the way down to individual components. Convert the
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