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ARM64: give TST aliases priority over ANDS.

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If an ANDS instruction has Rd == ZR it should be printed as TST since
its only effect is on the flags register NZCV.

This will be tested when the TableGen "should I print this Alias"
heuristic is fixed (very soon).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208959 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-05-16 09:41:08 +00:00
parent 22f4151e3b
commit 93185d186c
1 changed files with 10 additions and 10 deletions
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20
lib/Target/ARM64/ARM64InstrInfo.td
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@ -726,19 +726,19 @@ def AA_MVNWrs : InstAlias<"mvn $Wd, $Wm$sh",
def AA_MVNXrs : InstAlias<"mvn $Xd, $Xm$sh",
(ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh)>;
def : InstAlias<"tst $src1, $src2",
(ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
def : InstAlias<"tst $src1, $src2",
(ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
def AA_TSTWri : InstAlias<"tst $src1, $src2",
(ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
def AA_TSTXri : InstAlias<"tst $src1, $src2",
(ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
def : InstAlias<"tst $src1, $src2",
(ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
def : InstAlias<"tst $src1, $src2",
(ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>;
def AA_TSTWr: InstAlias<"tst $src1, $src2",
(ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
def AA_TSTXr: InstAlias<"tst $src1, $src2",
(ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>;
def : InstAlias<"tst $src1, $src2, $sh",
def AB_TSTWrs : InstAlias<"tst $src1, $src2$sh",
(ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh)>;
def : InstAlias<"tst $src1, $src2, $sh",
def AB_TSTXrs : InstAlias<"tst $src1, $src2$sh",
(ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh)>;