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[X86] Rename the X32_ADDR_ACCESS register class into LOW32_ADDR_ACCESS.

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This register class may be used by any ABIs that uses x86_64 ISA while
using 32-bit addresses, not just in X32 cases. Make sure the name
reflects that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268795 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet 2016-05-06 21:10:43 +00:00
parent a019a2c0f5
commit 93cbe6ed35
2 changed files with 12 additions and 8 deletions
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5
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -163,9 +163,10 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
if (Subtarget.isTarget64BitLP64())
return &X86::GR64RegClass;
// If the target is 64bit but we have been told to use 32bit addresses,
// we can still use RIP-relative addresses.
// we can still use 64-bit register as long as we know the high bits
// are zeros.
// Reflect that in the returned register class.
return Is64Bit ? &X86::X32_ADDR_ACCESSRegClass : &X86::GR32RegClass;
return Is64Bit ? &X86::LOW32_ADDR_ACCESSRegClass : &X86::GR32RegClass;
case 1: // Normal GPRs except the stack pointer (for encoding reasons).
if (Subtarget.isTarget64BitLP64())
return &X86::GR64_NOSPRegClass;

15
lib/Target/X86/X86RegisterInfo.td
View File

@ -415,14 +415,17 @@ def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32,
def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
(and GR64_NOREX, GR64_NOSP)>;
// Register classes used for X32 address accesses.
// In X32 mode it is fine to use RIP as we are sure the 32 high bits
// are not set.
// We do not need variants for NOSP as RIP is not allowed there.
// Register classes used for ABIs that use 32-bit address accesses,
// while using the whole x84_64 ISA.
// In such cases, it is fine to use RIP as we are sure the 32 high
// bits are not set. We do not need variants for NOSP as RIP is not
// allowed there.
// Alignment is 64 because we have RIP.
// FIXME: We could allow all 64bit registers, but we would need
// something to check that the 32 high bits are not set.
def X32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>;
// something to check that the 32 high bits are not set,
// which we do not have right now.
def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>;
// A class to support the 'A' assembler constraint: EAX then EDX.
def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;