mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-15 16:09:02 +00:00
Fold X+Y -> X|Y when safe. This implements:
Regression/CodeGen/PowerPC/and_add.ll a case that occurs with dynamic allocas of constant size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26727 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
f4f5f6bca8
commit
947c28935d
@ -714,9 +714,27 @@ SDOperand DAGCombiner::visitADD(SDNode *N) {
|
||||
// fold (A+(B-A)) -> B
|
||||
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
|
||||
return N1.getOperand(0);
|
||||
//
|
||||
|
||||
if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
|
||||
return SDOperand();
|
||||
|
||||
// fold (a+b) -> (a|b) iff a and b share no bits.
|
||||
if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
|
||||
uint64_t LHSZero, LHSOne;
|
||||
uint64_t RHSZero, RHSOne;
|
||||
uint64_t Mask = MVT::getIntVTBitMask(VT);
|
||||
TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
|
||||
if (LHSZero) {
|
||||
TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
|
||||
|
||||
// If all possibly-set bits on the LHS are clear on the RHS, return an OR.
|
||||
// If all possibly-set bits on the RHS are clear on the LHS, return an OR.
|
||||
if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
|
||||
(LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
|
||||
return DAG.getNode(ISD::OR, VT, N0, N1);
|
||||
}
|
||||
}
|
||||
|
||||
return SDOperand();
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user