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Implement setcc correctly for G5 and non-G5 systems

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23060 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-25 21:39:42 +00:00
parent 64906a06b3
commit 957fcfbd89
1 changed files with 17 additions and 11 deletions
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28
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -1087,17 +1087,23 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
SDOperand CCReg = SDOperand CCReg =
SelectCC(Select(N->getOperand(0)), Select(N->getOperand(1)), CC); SelectCC(Select(N->getOperand(0)), Select(N->getOperand(1)), CC);
SDOperand IntCR; SDOperand IntCR;
if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor()) {
IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CCReg); // Force the ccreg into CR7.
} else { SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
assert(0 && "Not imp yet!");
// FIXME: HOW DO WE DO THIS?? std::vector<MVT::ValueType> VTs;
#if 0 VTs.push_back(MVT::Other);
//SDOperand CR7Op = CurDAG->getCopyToReg(); VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg); std::vector<SDOperand> Ops;
BuildMI(BB, PPC::MFCR, 0, IntCR); Ops.push_back(CurDAG->getEntryNode());
#endif Ops.push_back(CR7Reg);
} Ops.push_back(CCReg);
CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
else
IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
if (!Inv) { if (!Inv) {
CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, IntCR, CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, IntCR,