From 95b39550344bad0d15d1ffa7afc300eb1533ed19 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Tue, 24 Apr 2007 21:13:23 +0000 Subject: [PATCH] Assertion when using a 1-element vector for an add operation. Get the real vector type in this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36402 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 6ce909b6ba8..22b08d23f24 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -308,19 +308,22 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { const VectorType *PTy = cast(V->getType()); unsigned NumElts = PTy->getNumElements(); MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); + MVT::ValueType VecTy = getVectorType(EltTy, NumElts); // Divide the input until we get to a supported size. This will always // end with a scalar if the target doesn't support vectors. - while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) { + while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) { NumElts >>= 1; NumVectorRegs <<= 1; } - if (NumElts == 1) + + // Check that VecTy isn't a 1-element vector. + if (NumElts == 1 && VecTy == MVT::Other) VT = EltTy; else - VT = getVectorType(EltTy, NumElts); + VT = VecTy; } - + // The common case is that we will only create one register for this // value. If we have that case, create and return the virtual register. unsigned NV = TLI.getNumElements(VT);