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Refactor the tablegen DAGISelEmitter code for outputing calls to
getTargetNode and SelectNodeTo to reduce duplication, and to make some of the getTargetNode code available to SelectNodeTo. Use SelectNodeTo instead of getTargetNode in several new interesting cases, as it mutates nodes in place instead of creating new ones. This triggers some scheduling behavior differences due to nodes being presented to the scheduler in a different order. Some of the arbitrary scheduling decisions it makes are now arbitrarily made differently. This is visible in CodeGen/PowerPC/LargeAbsoluteAddr.ll, where a trivial scheduling difference led to a trivial register allocation difference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53203 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
parent
667a68b96a
commit
95d110920e
@ -1,7 +1,7 @@
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; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin | \
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; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin | \
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; RUN: grep {stw r3, 32751}
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; RUN: grep {stw r2, 32751}
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; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin | \
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; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin | \
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; RUN: grep {stw r3, 32751}
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; RUN: grep {stw r2, 32751}
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; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin | \
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; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin | \
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; RUN: grep {std r2, 9024}
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; RUN: grep {std r2, 9024}
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@ -18,6 +18,7 @@
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/Streams.h"
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#include "llvm/Support/Streams.h"
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#include <algorithm>
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#include <algorithm>
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#include <deque>
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using namespace llvm;
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -1033,230 +1034,236 @@ public:
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}
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}
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unsigned ResNo = TmpNo++;
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unsigned ResNo = TmpNo++;
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if (!isRoot || InputHasChain || NodeHasChain || NodeHasOutFlag ||
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NodeHasOptInFlag || HasImpResults) {
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std::string Code;
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std::string Code2;
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std::string NodeName;
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if (!isRoot) {
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NodeName = "Tmp" + utostr(ResNo);
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Code2 = "SDOperand " + NodeName + "(";
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} else {
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NodeName = "ResNode";
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if (!ResNodeDecled) {
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Code2 = "SDNode *" + NodeName + " = ";
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ResNodeDecled = true;
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} else
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Code2 = NodeName + " = ";
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}
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Code += "CurDAG->getTargetNode(Opc" + utostr(OpcNo);
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unsigned OpsNo = OpcNo;
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unsigned OpsNo = OpcNo;
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std::string CodePrefix;
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emitOpcode(II.Namespace + "::" + II.TheDef->getName());
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bool ChainAssignmentNeeded = NodeHasChain && !isRoot;
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std::deque<std::string> After;
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// Output order: results, chain, flags
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std::string NodeName;
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// Result types.
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if (!isRoot) {
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if (NumResults > 0 && N->getTypeNum(0) != MVT::isVoid) {
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NodeName = "Tmp" + utostr(ResNo);
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Code += ", VT" + utostr(VTNo);
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CodePrefix = "SDOperand " + NodeName + "(";
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emitVT(getEnumName(N->getTypeNum(0)));
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}
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// Add types for implicit results in physical registers, scheduler will
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// care of adding copyfromreg nodes.
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for (unsigned i = 0; i < NumDstRegs; i++) {
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Record *RR = DstRegs[i];
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if (RR->isSubClassOf("Register")) {
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MVT::SimpleValueType RVT = getRegisterValueType(RR, CGT);
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Code += ", " + getEnumName(RVT);
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}
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}
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if (NodeHasChain)
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Code += ", MVT::Other";
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if (NodeHasOutFlag)
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Code += ", MVT::Flag";
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// Inputs.
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if (IsVariadic) {
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for (unsigned i = 0, e = AllOps.size(); i != e; ++i)
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emitCode("Ops" + utostr(OpsNo) + ".push_back(" + AllOps[i] + ");");
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AllOps.clear();
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// Figure out whether any operands at the end of the op list are not
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// part of the variable section.
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std::string EndAdjust;
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if (NodeHasInFlag || HasImpInputs)
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EndAdjust = "-1"; // Always has one flag.
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else if (NodeHasOptInFlag)
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EndAdjust = "-(HasInFlag?1:0)"; // May have a flag.
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emitCode("for (unsigned i = NumInputRootOps + " + utostr(NodeHasChain) +
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", e = N.getNumOperands()" + EndAdjust + "; i != e; ++i) {");
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emitCode(" AddToISelQueue(N.getOperand(i));");
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emitCode(" Ops" + utostr(OpsNo) + ".push_back(N.getOperand(i));");
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emitCode("}");
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}
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// Generate MemOperandSDNodes nodes for each memory accesses covered by
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// this pattern.
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if (II.isSimpleLoad | II.mayLoad | II.mayStore) {
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std::vector<std::string>::const_iterator mi, mie;
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for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
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emitCode("SDOperand LSI_" + *mi + " = "
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"CurDAG->getMemOperand(cast<MemSDNode>(" +
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*mi + ")->getMemOperand());");
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if (IsVariadic)
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emitCode("Ops" + utostr(OpsNo) + ".push_back(LSI_" + *mi + ");");
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else
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AllOps.push_back("LSI_" + *mi);
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}
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}
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if (NodeHasChain) {
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if (IsVariadic)
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emitCode("Ops" + utostr(OpsNo) + ".push_back(" + ChainName + ");");
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else
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AllOps.push_back(ChainName);
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}
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if (IsVariadic) {
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if (NodeHasInFlag || HasImpInputs)
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emitCode("Ops" + utostr(OpsNo) + ".push_back(InFlag);");
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else if (NodeHasOptInFlag) {
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emitCode("if (HasInFlag)");
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emitCode(" Ops" + utostr(OpsNo) + ".push_back(InFlag);");
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}
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Code += ", &Ops" + utostr(OpsNo) + "[0], Ops" + utostr(OpsNo) +
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".size()";
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} else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs)
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AllOps.push_back("InFlag");
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unsigned NumOps = AllOps.size();
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if (NumOps) {
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if (!NodeHasOptInFlag && NumOps < 4) {
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for (unsigned i = 0; i != NumOps; ++i)
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Code += ", " + AllOps[i];
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} else {
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std::string OpsCode = "SDOperand Ops" + utostr(OpsNo) + "[] = { ";
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for (unsigned i = 0; i != NumOps; ++i) {
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OpsCode += AllOps[i];
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if (i != NumOps-1)
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OpsCode += ", ";
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}
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emitCode(OpsCode + " };");
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Code += ", Ops" + utostr(OpsNo) + ", ";
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if (NodeHasOptInFlag) {
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Code += "HasInFlag ? ";
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Code += utostr(NumOps) + " : " + utostr(NumOps-1);
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} else
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Code += utostr(NumOps);
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}
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}
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if (!isRoot)
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Code += "), 0";
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emitCode(Code2 + Code + ");");
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if (NodeHasChain) {
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// Remember which op produces the chain.
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if (!isRoot)
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emitCode(ChainName + " = SDOperand(" + NodeName +
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".Val, " + utostr(NumResults+NumDstRegs) + ");");
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else
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emitCode(ChainName + " = SDOperand(" + NodeName +
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", " + utostr(NumResults+NumDstRegs) + ");");
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}
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if (!isRoot) {
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NodeOps.push_back("Tmp" + utostr(ResNo));
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return NodeOps;
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}
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bool NeedReplace = false;
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if (NodeHasOutFlag) {
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if (!InFlagDecled) {
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emitCode("SDOperand InFlag(ResNode, " +
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utostr(NumResults+NumDstRegs+(unsigned)NodeHasChain) + ");");
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InFlagDecled = true;
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} else
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emitCode("InFlag = SDOperand(ResNode, " +
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utostr(NumResults+NumDstRegs+(unsigned)NodeHasChain) + ");");
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}
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if (FoldedChains.size() > 0) {
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std::string Code;
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for (unsigned j = 0, e = FoldedChains.size(); j < e; j++)
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emitCode("ReplaceUses(SDOperand(" +
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FoldedChains[j].first + ".Val, " +
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utostr(FoldedChains[j].second) + "), SDOperand(ResNode, " +
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utostr(NumResults+NumDstRegs) + "));");
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NeedReplace = true;
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}
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if (NodeHasOutFlag) {
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if (FoldedFlag.first != "") {
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emitCode("ReplaceUses(SDOperand(" + FoldedFlag.first + ".Val, " +
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utostr(FoldedFlag.second) + "), InFlag);");
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} else {
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assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP));
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emitCode("ReplaceUses(SDOperand(N.Val, " +
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utostr(NumPatResults + (unsigned)InputHasChain)
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+"), InFlag);");
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}
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NeedReplace = true;
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}
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if (NeedReplace && InputHasChain)
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emitCode("ReplaceUses(SDOperand(N.Val, " +
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utostr(NumPatResults) + "), SDOperand(" + ChainName
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+ ".Val, " + ChainName + ".ResNo" + "));");
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// User does not expect the instruction would produce a chain!
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if ((!InputHasChain && NodeHasChain) && NodeHasOutFlag) {
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;
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} else if (InputHasChain && !NodeHasChain) {
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// One of the inner node produces a chain.
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if (NodeHasOutFlag)
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emitCode("ReplaceUses(SDOperand(N.Val, " + utostr(NumPatResults+1) +
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"), SDOperand(ResNode, N.ResNo-1));");
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emitCode("ReplaceUses(SDOperand(N.Val, " + utostr(NumPatResults) +
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"), " + ChainName + ");");
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}
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emitCode("return ResNode;");
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} else {
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} else {
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std::string Code = "return CurDAG->SelectNodeTo(N.Val, Opc" +
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NodeName = "ResNode";
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utostr(OpcNo);
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if (!ResNodeDecled) {
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if (N->getTypeNum(0) != MVT::isVoid)
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CodePrefix = "SDNode *" + NodeName + " = ";
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Code += ", VT" + utostr(VTNo);
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ResNodeDecled = true;
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if (NodeHasOutFlag)
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} else
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Code += ", MVT::Flag";
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CodePrefix = NodeName + " = ";
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if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs)
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AllOps.push_back("InFlag");
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unsigned NumOps = AllOps.size();
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if (NumOps) {
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if (!NodeHasOptInFlag && NumOps < 4) {
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for (unsigned i = 0; i != NumOps; ++i)
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Code += ", " + AllOps[i];
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} else {
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std::string OpsCode = "SDOperand Ops" + utostr(OpcNo) + "[] = { ";
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for (unsigned i = 0; i != NumOps; ++i) {
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OpsCode += AllOps[i];
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if (i != NumOps-1)
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OpsCode += ", ";
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}
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emitCode(OpsCode + " };");
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Code += ", Ops" + utostr(OpcNo) + ", ";
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Code += utostr(NumOps);
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}
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}
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emitCode(Code + ");");
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emitOpcode(II.Namespace + "::" + II.TheDef->getName());
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if (N->getTypeNum(0) != MVT::isVoid)
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emitVT(getEnumName(N->getTypeNum(0)));
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}
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}
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std::string Code = "Opc" + utostr(OpcNo);
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emitOpcode(II.Namespace + "::" + II.TheDef->getName());
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// Output order: results, chain, flags
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// Result types.
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if (NumResults > 0 && N->getTypeNum(0) != MVT::isVoid) {
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Code += ", VT" + utostr(VTNo);
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emitVT(getEnumName(N->getTypeNum(0)));
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}
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// Add types for implicit results in physical registers, scheduler will
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// care of adding copyfromreg nodes.
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for (unsigned i = 0; i < NumDstRegs; i++) {
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Record *RR = DstRegs[i];
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if (RR->isSubClassOf("Register")) {
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MVT::SimpleValueType RVT = getRegisterValueType(RR, CGT);
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Code += ", " + getEnumName(RVT);
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}
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}
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if (NodeHasChain)
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Code += ", MVT::Other";
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if (NodeHasOutFlag)
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Code += ", MVT::Flag";
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// Inputs.
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if (IsVariadic) {
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for (unsigned i = 0, e = AllOps.size(); i != e; ++i)
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emitCode("Ops" + utostr(OpsNo) + ".push_back(" + AllOps[i] + ");");
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AllOps.clear();
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// Figure out whether any operands at the end of the op list are not
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// part of the variable section.
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std::string EndAdjust;
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if (NodeHasInFlag || HasImpInputs)
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EndAdjust = "-1"; // Always has one flag.
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else if (NodeHasOptInFlag)
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EndAdjust = "-(HasInFlag?1:0)"; // May have a flag.
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emitCode("for (unsigned i = NumInputRootOps + " + utostr(NodeHasChain) +
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", e = N.getNumOperands()" + EndAdjust + "; i != e; ++i) {");
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emitCode(" AddToISelQueue(N.getOperand(i));");
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emitCode(" Ops" + utostr(OpsNo) + ".push_back(N.getOperand(i));");
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emitCode("}");
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}
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// Generate MemOperandSDNodes nodes for each memory accesses covered by
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// this pattern.
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if (II.isSimpleLoad | II.mayLoad | II.mayStore) {
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std::vector<std::string>::const_iterator mi, mie;
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for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
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emitCode("SDOperand LSI_" + *mi + " = "
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"CurDAG->getMemOperand(cast<MemSDNode>(" +
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*mi + ")->getMemOperand());");
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if (IsVariadic)
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emitCode("Ops" + utostr(OpsNo) + ".push_back(LSI_" + *mi + ");");
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else
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AllOps.push_back("LSI_" + *mi);
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}
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}
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if (NodeHasChain) {
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if (IsVariadic)
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emitCode("Ops" + utostr(OpsNo) + ".push_back(" + ChainName + ");");
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else
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AllOps.push_back(ChainName);
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}
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if (IsVariadic) {
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if (NodeHasInFlag || HasImpInputs)
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emitCode("Ops" + utostr(OpsNo) + ".push_back(InFlag);");
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else if (NodeHasOptInFlag) {
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emitCode("if (HasInFlag)");
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emitCode(" Ops" + utostr(OpsNo) + ".push_back(InFlag);");
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}
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Code += ", &Ops" + utostr(OpsNo) + "[0], Ops" + utostr(OpsNo) +
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".size()";
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} else if (NodeHasInFlag || NodeHasOptInFlag || HasImpInputs)
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AllOps.push_back("InFlag");
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unsigned NumOps = AllOps.size();
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if (NumOps) {
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if (!NodeHasOptInFlag && NumOps < 4) {
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|
for (unsigned i = 0; i != NumOps; ++i)
|
||||||
|
Code += ", " + AllOps[i];
|
||||||
|
} else {
|
||||||
|
std::string OpsCode = "SDOperand Ops" + utostr(OpsNo) + "[] = { ";
|
||||||
|
for (unsigned i = 0; i != NumOps; ++i) {
|
||||||
|
OpsCode += AllOps[i];
|
||||||
|
if (i != NumOps-1)
|
||||||
|
OpsCode += ", ";
|
||||||
|
}
|
||||||
|
emitCode(OpsCode + " };");
|
||||||
|
Code += ", Ops" + utostr(OpsNo) + ", ";
|
||||||
|
if (NodeHasOptInFlag) {
|
||||||
|
Code += "HasInFlag ? ";
|
||||||
|
Code += utostr(NumOps) + " : " + utostr(NumOps-1);
|
||||||
|
} else
|
||||||
|
Code += utostr(NumOps);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!isRoot)
|
||||||
|
Code += "), 0";
|
||||||
|
|
||||||
|
bool NeedReplace = false;
|
||||||
|
if (!isRoot) {
|
||||||
|
NodeOps.push_back("Tmp" + utostr(ResNo));
|
||||||
|
} else {
|
||||||
|
|
||||||
|
if (NodeHasOutFlag) {
|
||||||
|
if (!InFlagDecled) {
|
||||||
|
After.push_back("SDOperand InFlag(ResNode, " +
|
||||||
|
utostr(NumResults+NumDstRegs+(unsigned)NodeHasChain) +
|
||||||
|
");");
|
||||||
|
InFlagDecled = true;
|
||||||
|
} else
|
||||||
|
After.push_back("InFlag = SDOperand(ResNode, " +
|
||||||
|
utostr(NumResults+NumDstRegs+(unsigned)NodeHasChain) +
|
||||||
|
");");
|
||||||
|
}
|
||||||
|
|
||||||
|
if (FoldedChains.size() > 0) {
|
||||||
|
std::string Code;
|
||||||
|
for (unsigned j = 0, e = FoldedChains.size(); j < e; j++)
|
||||||
|
After.push_back("ReplaceUses(SDOperand(" +
|
||||||
|
FoldedChains[j].first + ".Val, " +
|
||||||
|
utostr(FoldedChains[j].second) +
|
||||||
|
"), SDOperand(ResNode, " +
|
||||||
|
utostr(NumResults+NumDstRegs) + "));");
|
||||||
|
NeedReplace = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (NodeHasOutFlag) {
|
||||||
|
if (FoldedFlag.first != "") {
|
||||||
|
After.push_back("ReplaceUses(SDOperand(" + FoldedFlag.first +
|
||||||
|
".Val, " +
|
||||||
|
utostr(FoldedFlag.second) + "), InFlag);");
|
||||||
|
} else {
|
||||||
|
assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP));
|
||||||
|
After.push_back("ReplaceUses(SDOperand(N.Val, " +
|
||||||
|
utostr(NumPatResults + (unsigned)InputHasChain)
|
||||||
|
+"), InFlag);");
|
||||||
|
}
|
||||||
|
NeedReplace = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (NeedReplace && InputHasChain) {
|
||||||
|
After.push_back("ReplaceUses(SDOperand(N.Val, " +
|
||||||
|
utostr(NumPatResults) + "), SDOperand(" + ChainName
|
||||||
|
+ ".Val, " + ChainName + ".ResNo" + "));");
|
||||||
|
ChainAssignmentNeeded |= NodeHasChain;
|
||||||
|
}
|
||||||
|
|
||||||
|
// User does not expect the instruction would produce a chain!
|
||||||
|
if ((!InputHasChain && NodeHasChain) && NodeHasOutFlag) {
|
||||||
|
;
|
||||||
|
} else if (InputHasChain && !NodeHasChain) {
|
||||||
|
// One of the inner node produces a chain.
|
||||||
|
if (NodeHasOutFlag)
|
||||||
|
After.push_back("ReplaceUses(SDOperand(N.Val, " +
|
||||||
|
utostr(NumPatResults+1) +
|
||||||
|
"), SDOperand(ResNode, N.ResNo-1));");
|
||||||
|
After.push_back("ReplaceUses(SDOperand(N.Val, " +
|
||||||
|
utostr(NumPatResults) + "), " + ChainName + ");");
|
||||||
|
NeedReplace = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ChainAssignmentNeeded) {
|
||||||
|
// Remember which op produces the chain.
|
||||||
|
std::string ChainAssign;
|
||||||
|
if (!isRoot)
|
||||||
|
ChainAssign = ChainName + " = SDOperand(" + NodeName +
|
||||||
|
".Val, " + utostr(NumResults+NumDstRegs) + ");";
|
||||||
|
else
|
||||||
|
ChainAssign = ChainName + " = SDOperand(" + NodeName +
|
||||||
|
", " + utostr(NumResults+NumDstRegs) + ");";
|
||||||
|
|
||||||
|
After.push_front(ChainAssign);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Use getTargetNode or SelectNodeTo? The safe choice is getTargetNode,
|
||||||
|
// but SelectNodeTo can be faster.
|
||||||
|
//
|
||||||
|
// SelectNodeTo is not safe in a non-root context, or if there is any
|
||||||
|
// replacement of results needed.
|
||||||
|
//
|
||||||
|
// SelectNodeTo is not profitable if it would require a dynamically
|
||||||
|
// allocated operand list in a situation where getTargetNode would be
|
||||||
|
// able to reuse a co-allocated operand list (as in a unary, binary or
|
||||||
|
// ternary SDNode, for example).
|
||||||
|
//
|
||||||
|
if (!isRoot || NeedReplace ||
|
||||||
|
(!IsVariadic && AllOps.size() < 4 &&
|
||||||
|
Pattern->getNumChildren() + InputHasChain + NodeHasInFlag <
|
||||||
|
AllOps.size())) {
|
||||||
|
Code = "CurDAG->getTargetNode(" + Code;
|
||||||
|
} else {
|
||||||
|
Code = "CurDAG->SelectNodeTo(N.Val, " + Code;
|
||||||
|
}
|
||||||
|
if (isRoot) {
|
||||||
|
if (After.empty())
|
||||||
|
CodePrefix = "return ";
|
||||||
|
else
|
||||||
|
After.push_back("return ResNode;");
|
||||||
|
}
|
||||||
|
|
||||||
|
emitCode(CodePrefix + Code + ");");
|
||||||
|
for (unsigned i = 0, e = After.size(); i != e; ++i)
|
||||||
|
emitCode(After[i]);
|
||||||
|
|
||||||
return NodeOps;
|
return NodeOps;
|
||||||
} else if (Op->isSubClassOf("SDNodeXForm")) {
|
} else if (Op->isSubClassOf("SDNodeXForm")) {
|
||||||
assert(N->getNumChildren() == 1 && "node xform should have one child!");
|
assert(N->getNumChildren() == 1 && "node xform should have one child!");
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user