From 95eb470ce184e309082f24a35c19bf1de7bf10b9 Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Sun, 11 Oct 2009 19:14:21 +0000
Subject: [PATCH] Implement 'm' memory operand properly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83785 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 20 +++++++++++++++
 test/CodeGen/MSP430/inline-asm.ll        | 31 +++++++++++++++---------
 2 files changed, 40 insertions(+), 11 deletions(-)

diff --git a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
index 25287e9dcec..a603e07b02e 100644
--- a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
+++ b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
@@ -52,6 +52,10 @@ namespace {
       return "MSP430 DAG->DAG Pattern Instruction Selection";
     }
 
+    virtual bool
+    SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+                                 std::vector<SDValue> &OutOps);
+
     // Include the pieces autogenerated from the target description.
   #include "MSP430GenDAGISel.inc"
 
@@ -122,6 +126,22 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr,
 }
 
 
+bool MSP430DAGToDAGISel::
+SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+                             std::vector<SDValue> &OutOps) {
+  SDValue Op0, Op1;
+  switch (ConstraintCode) {
+  default: return true;
+  case 'm':   // memory
+    if (!SelectAddr(Op, Op, Op0, Op1))
+      return true;
+    break;
+  }
+
+  OutOps.push_back(Op0);
+  OutOps.push_back(Op1);
+  return false;
+}
 
 /// InstructionSelect - This callback is invoked by
 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
diff --git a/test/CodeGen/MSP430/inline-asm.ll b/test/CodeGen/MSP430/inline-asm.ll
index e385718cf5a..2cc25a4835d 100644
--- a/test/CodeGen/MSP430/inline-asm.ll
+++ b/test/CodeGen/MSP430/inline-asm.ll
@@ -1,16 +1,25 @@
 ; RUN: llc < %s
-; PR4778
 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
-define signext i8 @__nesc_atomic_start() nounwind {
-entry:
-  %0 = tail call i16 asm sideeffect "mov    r2, $0", "=r"() nounwind ; <i16> [#uses=1]
-  %1 = trunc i16 %0 to i8                         ; <i8> [#uses=1]
-  %and3 = lshr i8 %1, 3                           ; <i8> [#uses=1]
-  %conv1 = and i8 %and3, 1                        ; <i8> [#uses=1]
-  tail call void asm sideeffect "dint", ""() nounwind
-  tail call void asm sideeffect "nop", ""() nounwind
-  tail call void asm sideeffect "", "~{memory}"() nounwind
-  ret i8 %conv1
+define void @imm() nounwind {
+        call void asm sideeffect "bic\09$0,r2", "i"(i16 32) nounwind
+        ret void
+}
+
+define void @reg(i16 %a) nounwind {
+        call void asm sideeffect "bic\09$0,r2", "r"(i16 %a) nounwind
+        ret void
+}
+
+@foo = global i16 0, align 2
+
+define void @immmem() nounwind {
+        call void asm sideeffect "bic\09$0,r2", "i"(i16* getelementptr(i16* @foo, i32 1)) nounwind
+        ret void
+}
+
+define void @mem() nounwind {
+        call void asm sideeffect "bic\09$0,r2", "m"(i16* @foo) nounwind
+        ret void
 }